JAJSR18 August   2023 SN74HC165B-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, VCC = 2 V
    7. 6.7  Timing Requirements, VCC = 4.5 V
    8. 6.8  Timing Requirements, VCC = 6 V
    9. 6.9  Switching Characteristics, VCC = 2 V
    10. 6.10 Switching Characteristics, VCC = 4.5 V
    11. 6.11 Switching Characteristics, VCC = 6 V
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Latching Logic
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Power Considerations
      2. 9.2.2 Input Considerations
      3. 9.2.3 Output Considerations
      4. 9.2.4 Detailed Design Procedure
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Requirements, VCC = 4.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Section 7)
PARAMETERTEST CONDITION25°C–55°C to 125°CUNIT
MINMAXMINMAX
fclock Clock frequency 31 21 MHz
twPulse durationCLK high or low1624ns
SH/ LD low1624
tsuSetup timeSH/ LD high before CLK↑1624ns
SER before CLK↑812
CLK INH before CLK↑2030
Data before SH/ LD↑2030
thHold timeSER data after CLK↑55ns
Parallel data after SH/ LD↑55
SH/ LD high after CLK↑55