JAJSO61F December   1982  – February 2022 SN54HC4020 , SN74HC4020

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • NS|16
  • N|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

5.5 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
VCC (V) TA = 25°C SN54HC4020 SN74HC4020 UNIT
MIN MAX MIN MAX MIN MAX
fCLK Clock frequency 2 5.5 3.7 4.3 MHz
4.5 28 19 22
6 33 22 25
tW Pulse duration CLK high or low 2 90 135 115 ns
4.5 18 27 23
6 15 23 20
CLR high 2 70 105 90
4.5 14 21 18
6 12 18 25
tsu Setup time, CLR inactive before CLK↓ 2 60 90 75 ns
4.5 12 18 15
6 10 15 13