JAJSIW9B March   2004  – April 2020 SN74HC74-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      SN74HC74-Q1 の機能ピン配置
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
        4. 9.2.1.4 Timing Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|14
  • PW|14
サーマルパッド・メカニカル・データ
発注情報

Parameter Measurement Information

  • Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
  • The outputs are measured one at a time, with one input transition per measurement.
SN74HC74-Q1 pmi-load-circuit-pp.gif
CL= 50 pF and includes probe and jig capacitance.
Figure 3. Load Circuit
SN74HC74-Q1 pmi-wf-clk-hold.gifFigure 5. Voltage Waveforms
Setup and Hold Times
SN74HC74-Q1 pmi-wf-delay-pp.gif
The maximum between tPLH and TPHL is used for tpd.
Figure 7. Voltage Waveforms
Propagation Delays
SN74HC74-Q1 pmi-wf-trans-times.gifFigure 4. Voltage Waveforms
Transition Times
SN74HC74-Q1 pmi-wf-clk-pls-wid.gifFigure 6. Voltage Waveforms
Pulse Width