SLOS739A July   2012  – March 2016 TAS5721

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - I/O Pin Characteristics
    6. 7.6  Master Clock Characteristics
    7. 7.7  Speaker Amplifier Characteristics
    8. 7.8  Headphone Amplifier and Line Driver Characteristics
    9. 7.9  Protection Characteristics
    10. 7.10 I2C Serial Control Port Requirements and Specifications
    11. 7.11 Serial Audio Port Timing
    12. 7.12 Typical Characteristics
      1. 7.12.1 Headphone Typical Characteristics
      2. 7.12.2 Line Driver Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Supply
      2. 9.3.2  I2C Address Selection and Fault Output
      3. 9.3.3  Device Protection System
        1. 9.3.3.1 Overcurrent (OC) Protection With Current Limiting
        2. 9.3.3.2 Overtemperature Protection
        3. 9.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      4. 9.3.4  Clock, Auto Detection, and PLL
      5. 9.3.5  PWM Section
      6. 9.3.6  SSTIMER Functionality
      7. 9.3.7  2.1-Mode Support
        1. 9.3.7.1 Supply Pumping and Polarity Inversion for 2.1 Mode
      8. 9.3.8  PBTL-Mode Support
      9. 9.3.9  I2C Serial Control Interface
        1. 9.3.9.1 Single- and Multiple-Byte Transfers
        2. 9.3.9.2 Single-Byte Write
        3. 9.3.9.3 Multiple-Byte Write
        4. 9.3.9.4 Single-Byte Read
        5. 9.3.9.5 Multiple-Byte Read
      10. 9.3.10 Dynamic Range Control (DRC)
      11. 9.3.11 Bank Switching
      12. 9.3.12 Serial Data Interface
        1. 9.3.12.1 Serial Interface Control and Timing
          1. 9.3.12.1.1 I2S Timing
          2. 9.3.12.1.2 Left-Justified
          3. 9.3.12.1.3 Right-Justified
      13. 9.3.13 DirectPath Headphone/Line Driver
        1. 9.3.13.1 Using Headphone Amplifier in TAS5721
        2. 9.3.13.2 Using Line Driver Amplifier in TAS5721
    4. 9.4 Device Functional Modes
      1. 9.4.1 Output Mode and MUX Selection
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
        1. 9.5.1.1 I2C Device Address Change Procedure
      2. 9.5.2 26-Bit 3.23 Number Format
    6. 9.6 Register Maps
      1. 9.6.1  Clock Control Register (0x00)
      2. 9.6.2  Device ID Register (0x01)
      3. 9.6.3  Error Status Register (0x02)
      4. 9.6.4  System Control Register 1 (0x03)
      5. 9.6.5  Serial Data Interface Register (0x04)
      6. 9.6.6  System Control Register 2 (0x05)
      7. 9.6.7  Soft Mute Register (0x06)
      8. 9.6.8  Volume Registers (0x07, 0x08, 0x09, 0x0A)
      9. 9.6.9  Volume Configuration Register (0x0E)
      10. 9.6.10 Modulation Limit Register (0x10)
      11. 9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
      12. 9.6.12 Pwm Shutdown Group Register (0x19)
      13. 9.6.13 Start/stop Period Register (0x1A)
      14. 9.6.14 Oscillator Trim Register (0x1B)
      15. 9.6.15 BKND_ERR Register (0x1C)
      16. 9.6.16 Input Multiplexer Register (0x20)
      17. 9.6.17 Channel 4 Source Select Register (0x21)
      18. 9.6.18 PWM Output MUX Register (0x25)
      19. 9.6.19 DRC Control (0x46)
      20. 9.6.20 Bank Switch and EQ Control (0x50)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Component Selection and Hardware Connections
        2. 10.2.2.2 I2C Pullup Resistors
        3. 10.2.2.3 Digital I/O Connectivity
        4. 10.2.2.4 Recommended Startup and Shutdown Procedures
          1. 10.2.2.4.1 Recommended Use Model
            1. 10.2.2.4.1.1 Initialization Sequence
            2. 10.2.2.4.1.2 Normal Operation
            3. 10.2.2.4.1.3 Shutdown Sequence
            4. 10.2.2.4.1.4 Power-Down Sequence
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 DVDD and AVDD Supplies
    2. 11.2 PVDD Power Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DCA Package
48-Pin HTSSOP
Top View
TAS5721 PO_DCA_TAS5721_SLOS739.gif

Pin Functions

PIN TYPE(1) TERMINATION DESCRIPTION
NAME NO.
ADR/FAULT 20 DI/DO - Dual function terminal which sets the LSB of the I2C address to 0 if pulled to GND, 1 if pulled to DVDD. If configured to be a fault output by the methods described in I²C Address Selection and Fault Output, this terminal is pulled low when an internal fault occurs. A pull-up or pull-down resistor is required, as is shown in the Typical Application Circuit Diagrams.
AGND 36 P - Ground reference for analog circuitry(3)
AVDD 19 P - Power supply for internal analog circuitry
AVDD_REG1 18 P - Voltage regulator derived from AVDD supply(2)
AVDD_REG2 37 P - Voltage regulator derived from AVDD supply(2)
BSTRPx 3, 42, 46, 47 P - Connection points for the bootstrap capacitors, which are used to create a power supply for the high-side gate drive of the device
DGND 35 P - Ground reference for digital circuitry(3)
DR_CN 12 P - Negative terminal for capacitor connection used in headphone amplifier and line driver charge pump
DR_CP 13 P - Positive terminal for capacitor connection used in headphone amplifier and line driver charge pump
DR_INx 7, 10 AI - Input for channel A or B of headphone amplifier or line driver
DR_OUTx 8, 9 AO - Output for channel A or B of headphone amplifier or line driver
DR_SD 39 DI - Places the headphone amplifier/line driver in shutdown when pulled low.
DR_VSS 11 P - Negative supply generated by charge pump for ground centered headphone and line driver output
DRVDD 14 P - Power supply for internal headphone and line driver circuitry
DVDD 34 P - Power supply for the internal digital circuitry
DVDD_REG 24 P - Voltage regulator derived from DVDD supply(2)
GVDD_REG 40 P - Voltage regulator derived from PVDD supply(2)
LRCLK 26 DI Pulldown Word select clock for the digital signal that is active on the input data line of the serial port
MCLK 21 DI Pulldown Master clock used for internal clock tree and sub-circuit and state machine clocking
NC 31 - - Not connected inside the device (all no connect terminals should be connected to ground)
OSC_GND 23 P - Ground reference for oscillator circuitry (this terminal should be connected to the system ground)
OSC_RES 22 AO - Connection point for oscillator trim resistor
PDN 25 DI Pullup Quick powerdown of the device that is used upon an unexpected loss of PVDD or DVDD power supply in order to quickly transition the outputs of the speaker amplifier to a 50/50 duty cycle. This quick powerdown feature avoids the audible anamolies that would occur as a result of loss of either of the supplies. If this pin is used to place the device into quick powerdown mode, the RST pin of the device must be toggled before the device is brought out of quick powerdown.
PGND 1 P - Ground reference for power device circuitry(3)
PLL_FLTM 16 AI/AO - Negative connection point for the PLL loop filter components
PLL_FLTP 17 AI/AO - Positive connection point for the PLL loop filter components
PLL_GND 15 P - Ground reference for PLL circuitry (this terminal should be connected to the system ground)
PowerPAD - P - Thermal and ground pad thatprovides both an electrical connection to the ground plane and a thermal path to the PCB for heat dissipation. This pad must be grounded to the system ground.
PVDD 4, 41 P - Power supply for internal power circuitry
RST 32 DI Pullup Places the device in reset when pulled low
SCL 30 DI - I2C serial control port clock
SCLK 27 DI Pulldown Bit clock for the digital signal that is active on the input data line of the serial data port
SDA 29 DI/DO - I2C serial control port data
SDIN 28 DI Pulldown Data line to the serial data port
SPK_OUTx 2, 43, 45, 48 AO - Speaker amplifier outputs
SSTIMER 38 AI - Connection point for the capacitor that is used by the ramp timing circuit, as described in Output Mode and MUX Selection
TEST1 5 DO - Used by TI for testing during device production (this terminal must be left floating)
TEST2 6 DO - Used by TI for testing during device production (this terminal must be left floating)
TEST3 33 DI - Used by TI for testing during device production (this terminal must be connected to GND)
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.
(3) This terminal should be connected to the system ground