JAJSF33C August   2017  – February 2023 THS3491

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Bare Die Information
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: VS = ±15 V
    6. 8.6 Electrical Characteristics: VS = ±7.5 V
    7. 8.7 Typical Characteristics: ±15 V
    8. 8.8 Typical Characteristics: ±7.5 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Down (PD) Pin
      2. 9.3.2 Power-Down Reference (REF) Pin
      3. 9.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 9.4 Device Functional Modes
      1. 9.4.1 Wideband Noninverting Operation
      2. 9.4.2 Wideband, Inverting Operation
      3. 9.4.3 Single-Supply Operation
      4. 9.4.4 Maximum Recommended Output Voltage
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driving Capacitive Loads
      2. 10.1.2 Video Distribution
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
          1. 10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
          2. 10.4.1.1.2 Power Dissipation and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-5B1F9A32-B5AF-47BD-A643-68FEBD3C6449-low.gif
NC - no internal connection
Figure 6-1 DDA Package, 8-Pin HSOIC With PowerPAD (Top View)
GUID-F4B0C177-18EB-4884-AD0E-95BEC9BDD34D-low.gif
NC - no internal connection
Figure 6-2 RGT Package, 16-Pin VQFN With Exposed Thermal Pad (Top View)
Table 6-1 Pin Functions
PIN (1) TYPE (2) DESCRIPTION
NAME HSOIC VQFN
FB — 1 O Input side feedback pin
GND — 5 GND Ground, PD logic reference on the VQFN-16 (RGT) package
NC 5 2, 9, 12, 15 — No connect (there is no internal connection). Recommended connection to a heat spreading plane, typically GND.
PD 8 16 I Amplifier power down: low = amplifier disabled, high (default) = amplifier enabled
REF 1 — I PD logic reference on the SOIC-8 (DDA) package. Typically connected to GND.
TJ_SENSE — 6 O Voltage proportional to die temperature
VIN– 2 3 I Inverting input
VIN+ 3 4 I Noninverting input
VOUT 6 10, 11 O Amplifier output
–VS 4 7, 8 P Negative power supply
+VS 7 13, 14 P Positive power supply
Thermal pad — Thermal pad. Electrically isolated from the device. Recommended connection to a heat spreading plane, typically GND.
(1) Both packages include a backside thermal pad. The thermal pad can be connected to a heat spreading plane that can be at any voltage because the device die is electrically isolated from this metal plate. The thermal pad can also be unused (not connected to any heat spreading plane or voltage) giving higher thermal impedance.
(2) GND = ground, I = input, O = output, P = power