JAJSI95 December   2019 TL16C750E

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. 7.1      ESD Ratings
    3. Table 2. Recommended Operating Conditions
    4. Table 3. Thermal Information
    5. Table 4. Electrical Characteristics
    6. Table 5. Timing Requirements
    7. 7.2      Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  UART Modes
      2. 9.3.2  Trigger Levels
      3. 9.3.3  Hardware Flow Control
      4. 9.3.4  Auto-RTS
      5. 9.3.5  Auto-CTS
      6. 9.3.6  Software Flow Control
      7. 9.3.7  Software Flow Control Example
      8. 9.3.8  Reset
      9. 9.3.9  Interrupts
      10. 9.3.10 Interrupt Mode Operation
      11. 9.3.11 Polled Mode Operation
      12. 9.3.12 Break and Timeout Conditions
      13. 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
      14. 9.3.14 Fractional Divisor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Interface Mode
        1. 9.4.1.1 IOR Used (MODE = VCC)
        2. 9.4.1.2 IOR Unused (MODE = GND)
      2. 9.4.2 DMA Signaling
        1. 9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)
        2. 9.4.2.2 Block DMA Transfers (DMA Mode 1)
      3. 9.4.3 Sleep Mode
    5. 9.5 Register Maps
      1. 9.5.1  Registers Operations
      2. 9.5.2  Receiver Holding Register (RHR)
      3. 9.5.3  Transmit Holding Register (THR)
      4. 9.5.4  FIFO Control Register (FCR)
      5. 9.5.5  Line Control Register (LCR)
      6. 9.5.6  Line Status Register (LSR)
      7. 9.5.7  Modem Control Register (MCR)
      8. 9.5.8  Modem Status Register (MSR)
      9. 9.5.9  Interrupt Enable Register (IER)
      10. 9.5.10 Interrupt Identification Register (IIR)
      11. 9.5.11 Enhanced Feature Register (EFR)
      12. 9.5.12 Divisor Latches (DLL, DLH, DLF)
      13. 9.5.13 Transmission Control Register (TCR)
      14. 9.5.14 Trigger Level Register (TLR)
      15. 9.5.15 FIFO Ready Register
      16. 9.5.16 Alternate Function Register (AFR)
      17. 9.5.17 RS-485 Mode
      18. 9.5.18 IrDA Overview
      19. 9.5.19 IrDA Encoder Function
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Set the desired baud rate
        2. 10.2.2.2 Reset the fifos
        3. 10.2.2.3 Sending data on the bus
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PFB Package
48-Pin TQFP
Top View
N.C. – No internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
A0 28 I Address bit 0 select. Internal registers address selection. Refer to Figure 30 for register address map.
A1 27 I Address bit 1 select. Internal registers address selection. Refer to Figure 30 for register address map.
A2 26 I Address bit 2 select. Internal registers address selection. Refer to Figure 30 for register address map.
CD 40 I Carrier detect (active low). A low on these pins indicates that a carrier has been detected by the modem.
CS 11 I Chip select. When CS is low, this input enables the ACE. When this input is high, the ACE remains inactive. When MODE is pulled low for "IOR Unused" mode, this will be pulled low and the state of IOW is read to determine if the transaction is a read or a write
CTS 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (ΔCTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.
D0, D1, D2
D3, D4, D5, D6, D7		 43, 44, 45
46, 47, 2, 3, 4		 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.
DSR 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (ΔDSR) of the modem status register indicates DSR has changed levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is generated.
DTR 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit. These pins can also be used in the RS-485 mode to control an external RS-485 driver or transceiver.
MODE 10 I Interface mode select pin. This pin must be tied to VCC or to GND. If MODE is pulled to VCC, IOR is used in communication. If MODE is pulled to GND, IOR is NOT used for communication. Only the state of IOW is sampled when CS is toggled low to determine if the transaction is a read or a write. In this mode, IOR must be connected to VCC
VSS 18 GND Power Reference
INT 30 O Interrupt. When active, INT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.
IOR 19 I Read inputs. When IOR is active (low) while the ACE is selected, the CPU is allowed to read status information or data from ACE register.
IOW 16 I Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0 through D7) from the external CPU to an internal register that is defined by address bits A0 through A2.
NC 1, 5, 6, 9, 12, 13, 17, 20, 21, 22, 24, 25, 34, 36, 37, 48 No internal connection
OP 31 O The state of this pin is defined by the user through the software settings of the MCR register, bit 3. INT is set to active mode and OP to logic 0 when the MCR-3 is set to logic 1. INT is set to the 3-state mode and OP to a logic 1 when MCR-3 is set to a logic 0
RESET 35 I Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the receiver input are disabled during reset time.
RI 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.
RTS 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic
RX 7 I Receive data input. During the local loopback mode, this RX input pin is disabled and TX data is internally connected to the UART RX input internally. During normal mode, RX should be held high when no data is being received. This input also can be used in IrDA mode. For more information, see IrDA Overview.
RXRDY 29 O Receive ready (active low). RXRDY goes low when the trigger level has been reached or a timeout interrupt occurs. It go high when the RX FIFO is empty or there is an error in RX FIFO.
TX 8 O Transmit data. This output is associated with serial transmit data from the TL16C750E device. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.
TXRDY 23 O Transmit ready (active low). TXRDY goes low when there are a trigger level number of spaces available. They go high when the TX buffer is full.
VCC 42 PWR Power supply inputs
XTAL1 14 I Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 27). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
XTAL2 15 O Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output or buffered clock output.