JAJSGP7B May   2012  – December 2018 TLV320DAC3203

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, Bypass Outputs
    6. 6.6  Electrical Characteristics, Microphone Interface
    7. 6.7  Electrical Characteristics, Audio Outputs
    8. 6.8  Electrical Characteristics, LDO
    9. 6.9  Electrical Characteristics, Misc.
    10. 6.10 Electrical Characteristics, Logic Levels
    11. 6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
    12. 6.12 Typical DSP Timing Characteristics
    13. 6.13 I2C Interface Timing
    14. 6.14 SPI Interface Timing (See )
    15. 6.15 Typical Characteristics
      1. 6.15.1 Typical Characteristics, FFT
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Connections
        1. 7.3.1.1 Digital Pins
          1. 7.3.1.1.1 Multifunction Pins
        2. 7.3.1.2 Analog Pins
      2. 7.3.2 Analog Audio I/O
        1. 7.3.2.1 Analog Low Power Bypass
        2. 7.3.2.2 Headphone Outputs
      3. 7.3.3 Digital Microphone Inteface
        1. 7.3.3.1 ADC Processing Blocks — Overview
          1. 7.3.3.1.1 Processing Blocks
      4. 7.3.4 DAC
        1. 7.3.4.1 DAC Processing Blocks — Overview
      5. 7.3.5 Powertune
      6. 7.3.6 Digital Audio I/O Interface
      7. 7.3.7 Clock Generation and PLL
      8. 7.3.8 Control Interfaces
        1. 7.3.8.1 I2C Control
        2. 7.3.8.2 SPI Control
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

Combined with the advanced PowerTune technology, the device can cover operations from 8kHz mono voice playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony applications.

The playback path offers signal processing blocks for filtering and effects, true differential output signal, flexible mixing of DAC and analog input signals as well as programmable volume controls. The TLV320DAC3203 contains two high-power output drivers which can be configured in multiple ways, including stereo and mono BTL. The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used in a mobile environment. When used in a docked environment, power consumption typically is less of a concern and lowest possible noise is more important. With PowerTune the TLV320DAC3203 can address both cases.

The voltage supply range for the TLV320DAC3203 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, a low-dropout regulator (LDO) is integrated to generate the appropriate analog supply from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.1V–3.6V.

The required internal clock of the TLV320DAC3203 can be derived from multiple sources, including the MCLK, BCLK, GPIO pins or the output of internal PLL, where the input to the PLL again can be derived from the MCLK, BCLK or GPIO pins. Although using the internal, fractional PLL ensures the availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.