JAJSD83C May 2017 – October 2019 TMP464
PRODUCTION DATA.
The TMP464 device is compatible with the I2C or SMBus interface. In I2C or SMBus protocol, the device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions.
To address a specific device, a start condition is initiated. A start condition is indicated by pulling the data line (SDA) from a high-to-low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the addressed slave responds to the master by generating an acknowledge (ACK) bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit (ACK). During data transfer, SDA must remain stable when SCL is high. A change in SDA when SCL is high is interpreted as a control signal. The TMP464 device has a word register structure (16-bit wide), with data writes always requiring two bytes. Data transfer occurs during the ACK at the end of the second byte.
After all data are transferred, the master generates a stop condition. A stop condition is indicated by pulling SDA from low to high when SCL is high.