SLOS654D August   2009  – December 2016 TPA3112D1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics, VCC = 24 V
    6. 6.6 DC Characteristics, VCC = 12 V
    7. 6.7 AC Characteristics, VCC = 24 V
    8. 6.8 AC Characteristics, VCC = 12 V
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Setting Via Gain0 And Gain1 Inputs
      2. 7.3.2 SD Operation
      3. 7.3.3 PLIMIT
      4. 7.3.4 GVDD Supply
      5. 7.3.5 DC Detect
      6. 7.3.6 Short-Circuit Protection And Automatic Recovery Feature
      7. 7.3.7 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPA3112D1 Modulation Scheme
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Ferrite Bead Filter Considerations
        2. 8.2.2.2 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
        3. 8.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 8.2.2.4 Input Resistance
        5. 8.2.2.5 Input Capacitor, CI
        6. 8.2.2.6 BSN and BSP Capacitors
        7. 8.2.2.7 Differential Inputs
        8. 8.2.2.8 Using Low-ESR Capacitors
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Recieving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout

Layout Guidelines

The TPA3112D1 can be used with a small, inexpensive ferrite bead output filter for most applications. However, because the Class-D switching edges are very fast, take care when planning the layout of the printed-circuit board. The following suggestions help to meet EMC requirements.

  • Decoupling capacitors: The high-frequency decoupling capacitors must be placed as close to the PVCC and AVCC pins as possible. Large, 220-µF or greater, bulk power supply decoupling capacitors must be placed near the TPA3112D1 on the PVCC supplies. Local, high-frequency bypass capacitors must be placed as close to the PVCC pins as possible. These capacitors can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good-quality, low-ESR ceramic capacitor from 220 pF to 1000 pF and a larger mid-frequency capacitor from 0.1 µF to 1 µF also of good quality to the PVCC connections at each end of the chip.
  • Keep the current loop from each of the outputs through the ferrite bead and the small filter capacitor and back to PGND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
  • Output filter: The ferrite EMI filter (Figure 20) must be placed as close to the output pins as possible for the best EMI performance. The LC filter (Figure 18 and Figure 19) must be placed close to the outputs. The capacitors used in both the ferrite and LC filters must be grounded to power ground.
  • Thermal Pad: The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land must be 6.46 mm by 2.35 mm. Seven rows of solid vias, three vias per row, 0.33-mm or 13-mils diameter, must be equally spaced underneath the thermal land. The vias must connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See PowerPAD™ Thermally Enhanced package (SLMA002) for more information about using the HTSSOP thermal pad. For recommended PCB footprints, see mechanical pages appended to the end of this data sheet.

For an example layout, see the TPA3112D1EVM Audio Amplifier Evaluation Board User's Guide (SLOU270). The EVM documentation is available on the TI website at http://www.ti.com/tool/TPA3112D1EVM.

Layout Example

TPA3112D1 BTL_layout_slos618.gif Figure 24. BTL Layout Example