SLOS700C January   2011  – April 2016 TPA6139A2

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Programmable Gain Settings
    7. 7.7 Typical Characteristics, Line Driver
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 DirectPath Headphone Driver
    4. 9.4 Device Functional Modes
      1. 9.4.1 Internal Undervoltage Detection
      2. 9.4.2 Pop-Free Power Up
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Capacitive Load
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Component Selection
          1. 10.2.2.1.1 Charge Pump
          2. 10.2.2.1.2 Decoupling Capacitors
          3. 10.2.2.1.3 Gain Setting
          4. 10.2.2.1.4 Input-Blocking Capacitors
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD to GND –0.3 4 V
Input voltage, VI VSS – 0.3 VDD + 0.3 V
MUTE to GND –0.3 VDD + 0.3 V
Maximum operating junction temperature, TJ –40 150 °C
Lead temperature 260 °C
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
TPA6139A2 IN PW PACKAGE
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except 2 and 13 ±4000 V
Pins 2 and 13 ±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
TPA6139A2 IN RGT PACKAGE
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except 1 and 12 ±4000 V
Pins 1 and 12 ±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range unless otherwise noted
MIN NOM MAX UNIT
VDD Supply voltage DC supply voltage 3 3.3 3.6 V
RL Load resistance 16 32 10000 Ω
VIL Low-level input voltage MUTE 38 40 43 %PVDD
VIH High-level input voltage MUTE 57 60 66 %PVDD
TA Free-air temperature –40 25 85 °C

7.4 Thermal Information

THERMAL METRIC(1) TPA6139A2 UNIT
PW (TSSOP) RGT (VQFN)
14 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 130 52 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49 71 °C/W
RθJB Junction-to-board thermal resistance 63 26 °C/W
ψJT Junction-to-top characterization parameter 3.6 3 °C/W
ψJB Junction-to-board characterization parameter 62 26 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 9.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VDD = 3.3 V, RLoad = 32 Ω, TA = 25°C, Charge pump: CCP = 1 μF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage VDD = 3.3 V, input AC-coupled 0.5 1 mV
PSRR Power-supply rejection ratio 70 80 dB
VOH High-level output voltage VDD = 3.3 V 3.1 V
VOL Low-level output voltage VDD = 3.3 V –3.05 V
Vuvp_on PVDD, under voltage detection 2.8 V
Vuvp_hysteresis PVDD, under voltage detection, hysteresis 200 mV
Fcp Charge pump switching frequency 350 kHz
|IIH| High-level input current, MUTE VDD = 3.3 V, VIH = VDD 1 µA
|IIL| Low-level input current, MUTE VDD = 3.3 V, VIL = 0 V 1 µA
I (VDD) Supply current, no load VDD, MUTE = 3.3 V 25 mA
Supply current, MUTED VDD = 3.3 V, MUTE = GND 25 mA
Tsd Thermal shutdown 150 °C
Thermal shutdown hysteresis 15 °C
PO Output Power, outputs in phase THD+N = 1%, f = 1 kHz, 32-Ω load 25 mW
VO Output Voltage, outputs in phase THD+N = 1%, f = 1 kHz, 32-Ω load 0.9 Vrms
THD+N = 1%, f = 1 kHz, 600-Ω load 2
THD+N Total Harmonic distortion plus noise f = 1kHz, 32-Ω load, Po = 25 mW, –1x gain 0.03%
THD+N Total Harmonic distortion plus noise f = 1kHz, 10-kΩ load, Vo = 2 Vrms, –1x gain 0.005%
ΔAV Gain matching Between left and right channels 0.25 dB
ZO Output impedance when muted MUTE = GND 1 Ω
Input to output attenuation when muted MUTE = GND 80 dB
SNR Signal to noise ratio A-weighted, AES17 filter, 1-Vrms ref 32-Ω load, –1x gain 99 dB
Signal to noise ratio A-weighted, AES17 filter, 2-Vrms ref 600-Ω load, –1x gain 105 dB
Vn Noise voltage A-weighted, AES17 filter, Gain = –2x 12 µV
Slew rate 4.5 V/µs
Gbw Unity gain bandwidth 8 MHz
Crosstalk Channel to channel f = 1 kHz, Rload = 32 Ω, Po = 25 mW –85 dB
Vincm_pos Positive common-mode input voltage +2 V
Vincm_neg Negative common-mode input voltage –2 V
Ilim Output current limit 60 mA

7.6 Programmable Gain Settings

VDD = 3.3 V, Rload = 32 kΩ, TA = 25°C, Charge pump:= CCP 1 µF, CIN = 1 µF, 1x gain select (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R_Tol Gain programming resistor tolerance 2%
ΔAV Gain matching Between left and right channels 0.25 dB
Gain step tolerance 0.1 dB
Gain steps Gain resistor 2% tolerance 249k or higher –2 V/V
82k0 –1
49k2 –1.5
35k1 –2.3
27k3 –2.5
20k5 –3
15k4 –3.5
11k5 –4
9k09 –5
7k50 –5.6
6k19 –6.4
5k11 –8.3
3k90 –10
Input impedance Gain resistor 2% tolerance 249k or higher 37 kΩ
82k0 55
49k2 44
35k1 33
27k3 31
20k5 28
15k4 24
11k5 22
9k09 18
7k50 17
6k19 15
5k11 12
3k90 10
(1) If pin 12, GAIN, is left floating an internal pullup sets the gain to –2x.
Gain setting is latched during power up.

7.7 Typical Characteristics, Line Driver

VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 10 µF, Gain Step = –2 V/V (unless otherwise noted)
TPA6139A2 THDN_w_los700.gif
3.3 V, 100 kΩ, 1 kHz
Figure 1. THD+N vs Output Voltage
TPA6139A2 chan_sep_los700.gif
3.3 V, 5-kΩ load, 2 Vrms, Blue L to R, Red R to L
Figure 3. Channel Separation
TPA6139A2 gain_f_los700.gif Figure 5. Gain vs Frequency
TPA6139A2 mute_un_los700.gif Figure 7. Mute to Un-Mute
TPA6139A2 THDN_vo_los700.gif
3.3 V, 600-Ω load, 1 kHz
Figure 2. THD+N vs Output Voltage
TPA6139A2 fft_los700.gif Figure 4. FFT
TPA6139A2 THD_f_los700.gif Figure 6. Total Harmonic Distortion vs Frequency
TPA6139A2 un_mute_los700.gif Figure 8. Un-Mute to Mute