SLVSCX7A February   2015  – March 2015 TPS22958

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics (VBIAS = 5 V)
    6. 7.6  Electrical Characteristics (VBIAS = 3.3 V)
    7. 7.7  Electrical Characteristics (VBIAS = 2.5 V)
    8. 7.8  Switching Characteristics
    9. 7.9  Typical DC Characteristics
    10. 7.10 Typical AC Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 ON/OFF Control
      2. 9.3.2 Quick Output Discharge (QOD)
      3. 9.3.3 VIN and VBIAS Voltage Range
      4. 9.3.4 Adjustable Rise Time
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Capacitor (Optional)
      2. 10.1.2 Output Capacitor (Optional)
      3. 10.1.3 Power Supply Sequencing Without a GPIO Input
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 VIN to VOUT Voltage Drop
        2. 10.2.2.2 Inrush Current
        3. 10.2.2.3 Thermal Considerations
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

  • VIN and VOUT traces should be as short and wide as possible to accommodate for high current. When connecting the two VIN or VOUT pins together, an equal trace length should be used to avoid an unequal distribution of current through each pin.
  • Use vias under the exposed thermal pad to connect to the power ground plane for thermal relief during high current operation.
  • VIN pins should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
  • VOUT pins should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating. This capacitor should be placed as close to the device pins as possible.
  • The CT capacitor should be placed as close to the device pins as possible. The typical recommended CT capacitance is a capacitor of X5R or X7R dielectric rating with a rating of 25 V or higher.

12.2 Layout Example

TPS22958 TPS22958N layout_slvscx7.gif