JAJSEJ1B november   2017  – july 2020 TPS254900A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  FAULT Response
      2. 8.3.2  Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3  D+ and D– Protection
      4. 8.3.4  VBUS OVP Protection
      5. 8.3.5  Output and D+ or D– Discharge
      6. 8.3.6  Port Power Management (PPM)
        1. 8.3.6.1 Benefits of PPM
        2. 8.3.6.2 PPM Details
        3. 8.3.6.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
      7. 8.3.7  Overcurrent Protection
      8. 8.3.8  Undervoltage Lockout
      9. 8.3.9  Thermal Sensing
      10. 8.3.10 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 USB BC1.2 Specification Overview
      3. 8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
      4. 8.4.4 Charging Downstream Port (CDP) Mode
      5. 8.4.5 Client Mode
      6. 8.4.6 High-Bandwidth Data-Line Switch
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

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発注情報

8.4.1 Device Truth Table (TT)

The device truth table (Table 8-3) lists all valid combinations for both control pins (CTL1 and CTL2), and the corresponding charging mode. The TPS254900A-Q1 device monitors the CTL inputs and transitions to the charging mode to which it is commanded.

Table 8-3 Truth Table
CTL1CTL2CURRENT LIMIT SELECTEDMODESTATUS FOR LOAD DETECTCS FOR CABLE COMPENSATIONIMON FOR CURRENT MONITORFAULT REPORTNOTES
00N/AClient mode(1)OFFOFFOFFOFFPower switch is disabled, only analog switch is on.
01ILIM_LOSDPOFFONONONStandard SDP
10ILIM_LOSDP1(2)OFFONONON(3)No OUT discharge between CDP and SDP1 for PPM
11ILIM_HICDP(2)ONONONON
(1) No 5.1-kΩ resistor from BIAS to OUT (open between the pins), or OUT still has 5-V voltage from an external downstream port; client mode is still active.
(2) No OUT discharge when changing from 10 to 11 or from 11 to 10.
(3) A fault only trips OTSD, OUT, DP_IN, DM_IN, and OVP.