JAJSEJ1B november   2017  – july 2020 TPS254900A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  FAULT Response
      2. 8.3.2  Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3  D+ and D– Protection
      4. 8.3.4  VBUS OVP Protection
      5. 8.3.5  Output and D+ or D– Discharge
      6. 8.3.6  Port Power Management (PPM)
        1. 8.3.6.1 Benefits of PPM
        2. 8.3.6.2 PPM Details
        3. 8.3.6.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
      7. 8.3.7  Overcurrent Protection
      8. 8.3.8  Undervoltage Lockout
      9. 8.3.9  Thermal Sensing
      10. 8.3.10 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 USB BC1.2 Specification Overview
      3. 8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
      4. 8.4.4 Charging Downstream Port (CDP) Mode
      5. 8.4.5 Client Mode
      6. 8.4.6 High-Bandwidth Data-Line Switch
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

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発注情報

6.6 Switching Characteristics

Unless otherwise noted –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(IN). R(FAULT) = R(STATUS) = 10 kΩ, R(IMON) = 2.55 KΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
trOUT voltage rise timeV(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω1.051.753.1ms
tfOUT voltage fall time0.270.470.82ms
tonOUT voltage turnon timeV(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω7.511ms
toffOUT voltage turnoff time2.75ms
t(DCHG_S)Discharge hold time (mode change)Time V(OUT) < 0.7 V1.122.9s
t(IOS)OUT short-circuit response time(1)V(IN) = 5 V, R(SHORT) = 50 mΩ2µs
t(OC_OUT_FAULT)OUT FAULT deglitch timeBidirectional deglitch applicable to current-limit condition only (no deglitch assertion for OTSD)5.58.511.5ms
tpdAnalog switch propagation delay (1)V(IN) = 5 V0.14ns
t(SK)Analog switch skew between opposite transitions of the same port (tPHL – tPLH) (1)V(IN) = 5 V0.02ns
t(LD_SET)Load-detect set timeV(IN) = 5 V120210280ms
t(LD_RESET)Load-detect reset timeV(IN) = 5 V1.834.2s
t(OV_Data)DP_IN and DM_IN overvoltage protection response time5µs
t(OV_OUT)OUT overvoltage protection response time0.3µs
t(OV_D_FAULT)DP_IN and DM_IN FAULT-asserted degltich time111623ms
OUT FAULT-asserted degltich time111623ms
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.