JAJSHY1E September   2019  – March 2022 TPS25840-Q1 , TPS25842-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short-to-Battery Protection
        1. 10.3.11.1 V BUS and V CSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
      17. 10.3.17 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
      3. 10.4.3 Device Truth Table (TT)
      4. 10.4.4 USB Port Operating Modes
        1. 10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        2. 10.4.4.2 Charging Downstream Port (CDP) Mode
        3. 10.4.4.3 Client Mode
      5. 10.4.5 High-bandwidth Data-line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 サポート・リソース
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

GUID-F9FAE054-B30B-47D2-A570-484E7EFE9169-low.gifFigure 7-1 TPS25840QWRHBRQ1, TPS25842QWRHBRQ1 Package32-Pin (VQFN)Top View(1)
GUID-20210719-CA0I-ZCKJ-TWXX-NNJGRRSFXWG7-low.gifFigure 7-2 TPS25840QCWRHBRQ1, TPS25842QCWRHBRQ1 Package32-Pin (VQFN)Top View(2)
Table 7-1 Pin Functions
PINTYPE(3)I/ODESCRIPTION
NAMENO.
AGND16G-Analog ground terminal. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB.
BOOT32PBoot-strap capacitor connection for HS FET driver. Connect a high quality 100-nF capacitor from this pin to the SW pin.
BUS15AIVBUS discharge input. Connect to VBUS on USB Connector.
CSN/OUT13PINegative input of current sense amplifier, also buck output for internal voltage regulation.
CSP14PIPositive input of current sense amplifier.
CTRL15AILogic-level control inputs for device and system configuration (see Table 10-6).
CTRL26AILogic-level control inputs for device and system configuration (see Table 10-6).
DM_IN17ADM data line. Connect to USB connector.
DM_OUT8ADM data line. Connect to USB host controller.
DP_IN18ADP data line. Connect to USB connector.
DP_OUT7ADP data line. Connect to USB host controller.
EN/UVLO4AEnable pin. Do not float. High = on, Low = off. Can be tied to VIN. Precision enable input allows adjustable UVLO by external resistor divider.
FAULT24AOActive LOW open-drain output. Asserted during fault conditions (see Table 10-4). TI recommends series about 1-k ohm damping resistor for better signal quality.
ILIMIT12AExternal resistor used to set the current-limit threshold (see Table 10-2).
IMON11AExternal resistor used to set the max cable comp voltage at full load current.
IN1, 2, 3PIInput Supply to regulator. Connect high-quality bypass capacitors directly to this pin and PGND.
BUCK_ST23AOActive Low open-drain output. After BUCK_ST assert, the Buck converter begins to start up. At the same time, DP and DM data switch turn on accordingly.
LS_GD10AExternal NMOS gate driver. If TPS2584x-Q1 configured under average current limit mode, LS_GD pin must be pulled up through a 2.2-kΩ resistor (see Current Limit Sensing using RILIMIT).
PGND25, 26, 27GPower ground terminal. Connect to system ground and AGND. Connect to bypass capacitor with short wide traces.
N/C19, 22-Make no electrical connection.
RT/SYNC9AResistor Timing or External Clock input. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
SW28, 29, 30, 31PSwitching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to power inductor.
INT20AFor internal circuit, must connect a 5.1-K resistor to AGND.
VCC21POutput of internal bias supply. Used as supply to internal control circuits. Connect a high quality 2.2-µF capacitor from this pin to GND.
(1) For package drawing please refer to RHB0032R at the end of the data sheet.
(2) For package drawing please refer to RHB0032AA at the end of the data sheet.
(3) A = Analog, P = Power, G = Ground.