SLUSC26A May   2015  – February 2016 TPS54334

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Slope Compensation and Output Current
      4. 7.3.4  Bootstrap Voltage (BOOT) and Low Dropout Operation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Undervoltage Lockout
      9. 7.3.9  Slow Start
      10. 7.3.10 Safe Start-up into Pre-Biased Outputs
      11. 7.3.11 Power Good (PGOOD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overcurrent/Overvoltage/Thermal Protection
      2. 7.4.2 Thermal Shutdown
      3. 7.4.3 Small Signal Model for Loop Response
      4. 7.4.4 Small Signal Model for Peak Current Mode Control
      5. 7.4.5 Small Signal Model for Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS54334 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Switching Frequency
          2. 8.2.1.2.2 Output Voltage Set Point
          3. 8.2.1.2.3 Undervoltage Lockout Set Point
          4. 8.2.1.2.4 Input Capacitors
          5. 8.2.1.2.5 Output Filter Components
            1. 8.2.1.2.5.1 Inductor Selection
            2. 8.2.1.2.5.2 Capacitor Selection
          6. 8.2.1.2.6 Compensation Components
          7. 8.2.1.2.7 Bootstrap Capacitor
          8. 8.2.1.2.8 Power Dissipation Estimate
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The following design procedure can be used to select component values for the TPS54334. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process using the TPS54334.

8.2 Typical Applications

8.2.1 TPS54334 Application

TPS54334 simp_schem2_54334DRC_SLUSC26.gif Figure 18. Typical Application Schematic, TPS54334

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 4.2 to 24 V
Output voltage 3.3 V
Transient response, 1.5-A load step ΔVO = ±5 %
Input ripple voltage 400 mV
Output ripple voltage 30 mV
Output current rating 3 A
Operating Frequency 570 kHz

8.2.1.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS54334. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process using the TPS54334 device.

For this design example, use the input parameters listed in Table 1.

8.2.1.2.1 Switching Frequency

The switching frequency of the TPS54334 device is set at 570 kHz to match the internally set frequency of the TPS54334 device for this design.

8.2.1.2.2 Output Voltage Set Point

The output voltage of the TPS54334 device is externally adjustable using a resistor divider network. In the application circuit of Figure 18, this divider network is comprised of R5 and R6. Use Equation 13 and Equation 14 to calculate the relationship of the output voltage to the resistor divider.

Equation 13. TPS54334 new_eq4a_lvs839.gif
Equation 14. TPS54334 new_eq5a_lvs839.gif

Select a value of R5 to be approximately 31.6 kΩ. Slightly increasing or decreasing R5 can result in closer output-voltage matching when using standard value resistors. In this design, R5 = 31.6 kΩ and R6 = 10 kΩ which results in a 3.328-V output voltage. The 51.1-Ω resistor, R4, is provided as a convenient location to break the control loop for stability testing.

8.2.1.2.3 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) set point can be adjusted using the external-voltage divider network of R1 and R2. R1 is connected between the VIN and EN pins of the TPS54334 device. R2 is connected between the EN and GND pins. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the minimum input voltage is 4.2V, so the start-voltage threshold is set to 4.1 V and the stop-voltage threshold is set to VIN UVLO (3.7V). Use Equation 2 and Equation 3 to calculate the values for the upper and lower resistor values of R1 and R2.

8.2.1.2.4 Input Capacitors

The TPS54334 device requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value can be used as long as all other requirements are met; however a 10-μF capacitor has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54334 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design, a 10-μF, X7R dielectric capacitor rated for 35 V is used for the input decoupling capacitor. The ESR is approximately 2 mΩ, and the current rating is 3 A. Additionally, a small 0.1-μF capacitor is included for high frequency filtering.

Use Equation 15 to calculate the input ripple voltage (ΔVIN).

Equation 15. TPS54334 new_eq4_slvsc03.gif

where

  • CBULK is the bulk capacitor value
  • ƒSW is the switching frequency
  • IOUT(MAX) is the maximum load current
  • ESRMAX is the maximum series resistance of the bulk capacitor

The maximum RMS (root mean square) ripple current must also be checked. For worst case conditions, use Equation 16 to calculate ICIN(RMS).

Equation 16. TPS54334 new_eq5_lvs839.gif

In this case, the input ripple voltage is 138 mV and the RMS ripple current is 1.5 A.

NOTE

The actual input-voltage ripple is greatly affected by parasitics associated with the layout and the output impedance of the voltage source.

Design Requirements shows the actual input voltage ripple for this circuit which is larger than the calculated value. This measured value is still below the specified input limit of 400 mV. The maximum voltage across the input capacitors is VIN(MAX) + ΔVIN / 2. The selected bypass capacitor is rated for 35 V and the ripple current capacity is greater than 3 A. Both values provide ample margin. The maximum ratings for voltage and current must not be exceeded under any circumstance.

8.2.1.2.5 Output Filter Components

Two components must be selected for the output filter, the output inductor (LO) and CO. Because the TPS54334 device is an externally compensated device, a wide range of filter component types and values can be supported.

8.2.1.2.5.1 Inductor Selection

Use Equation 17 to calculate the minimum value of the output inductor (LMIN).

Equation 17. TPS54334 new_eq_lmin_slvsc03.gif

where

  • KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current

In general, the value of KIND is at the discretion of the designer; however, the following guidelines may be used. For designs using low-ESR output capacitors, such as ceramics, a value as high as KIND = 0.3 can be used. When using higher ESR output capacitors, KIND = 0.2 yields better results.

For this design example, use KIND = 0.3. The minimum inductor value is calculated as 5.6 μH. For this design, a standard value of 6.8 µH was selected for LMIN.

For the output filter inductor, the RMS current and saturation current ratings must not be exceeded. Use Equation 18 to calculate the RMS inductor current (IL(RMS)).

Equation 18. TPS54334 qa_ilms_slvsc03.gif

Use Equation 19 to calculate the peak inductor current (IL(PK)).

Equation 19. TPS54334 qa_ilpk_slvsc03.gif

For this design, the RMS inductor current is 3.01 A and the peak inductor current is 3.459 A. The selected inductor is a Vishay 6.8 μH, IHLP-4040DZ-01. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow so long as the other design requirements are met. Larger value inductors have lower AC current and result in lower output voltage ripple. Smaller inductor values increase AC current and output voltage ripple. In general, for the TPS54334 device, use inductors with values in the range of 0.68 μH to 100 μH.

8.2.1.2.5.2 Capacitor Selection

Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for the regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition from no load to full load. The regulator usually requires two or more clock cycles for the control loop to notice the change in load current and output voltage and to adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of drop in the output voltage. Use Equation 20 to calculate the minimum required output capacitance.

Equation 20. TPS54334 eq_co1_slvsc03.gif

where

  • ΔIOUT is the change in output current
  • ƒSW is the switching frequency of the regulator
  • ΔVOUT is the allowable change in the output voltage

For this example, the transient load response is specified as a 5% change in the output voltage, VOUT, for a load step of 1.5 A. For this example, ΔIOUT = 1.5 A and ΔVOUT = 0.05 × 3.3 = 0.165 V. Using these values results in a minimum capacitance of 31.9 μF. This value does not consider the ESR of the output capacitor in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Equation 21 calculates the minimum output capacitance required to meet the output voltage ripple specification. In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 21 yields 3.65 µF.

Equation 21. TPS54334 eq_co2_slvsc03.gif

where

  • ƒSW is the switching frequency
  • VOUTripple is the maximum allowable output voltage ripple
  • Iripple is the inductor ripple current

Use Equation 22 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple specification. Equation 22 indicates the ESR should be less than 40.9 mΩ. In this case, the ESR of the ceramic capacitor is much smaller than 40.9 mΩ.

Equation 22. TPS54334 eq_co3_slvsc03.gif

Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases this minimum value. For this example, two 22-μF 25-V X7R ceramic capacitors with 3 mΩ of ESR are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS value of the maximum ripple current. Use Equation 23 to calculate the RMS ripple current that the output capacitor must support. For this application, Equation 23 yields 106 mA for each capacitor.

Equation 23. TPS54334 new_eq11_slvsc03.gif

8.2.1.2.6 Compensation Components

Several possible methods exist to design closed loop compensation for DC-DC converters. For the ideal current-mode control, the design equations can be easily simplified. The power stage gain is constant at low frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is 0 degrees at low frequencies and begins to fall one decade below the modulator pole frequency reaching a minimum of –90 degrees which is one decade above the modulator pole frequency. Use Equation 24 to calculate the simple modulator pole (ƒp_mod).

Equation 24. TPS54334 comp_eq1_slvsc03.gif

For the TPS54334 device, most circuits have relatively high amounts of slope compensation. As more slope compensation is applied, the power stage characteristics deviate from the ideal approximations. The phase loss of the power stage will now approach –180 degrees, making compensation more difficult. The power stage transfer function can be solved but it requires a tedious calculation. Use the PSpice model to accurately model the power-stage gain and phase so that a reliable compensation circuit can be designed. Alternately, a direct measurement of the power stage characteristics can be used which is the technique used in this design procedure. For this design, the calculated values are as follows:

L1 = 6.8 µH

C6 and C7 = 22 µF

ESR = 3 mΩ

Figure 19 shows the power stage characteristics.

TPS54334 D016a_SLUSC26.gif Figure 19. Power Stage Gain and Phase Characteristics

For this design, the intended crossover frequency is 54.26 kHz (an actual measured data point exists for that frequency). From the power stage gain and phase plots, the gain at 54.26 kHz is –2.088 dB and the phase is about –121 degrees. For 60 degrees of phase margin, additional phase boost from a feed-forward capacitor in parallel with the upper resistor of the voltage set point divider is needed. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at crossover. Use Equation 25 to calculate the required value of R3.

Equation 25. TPS54334 Eq25_R3_SLUSC26.gif

To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 54.26 kHz. Use Equation 26 to calculate the required value for C4.

Equation 26. TPS54334 C4_slvsc03.gif

To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 54.26 kHz. The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. Use Equation 27 to calculate the value of C5.

Equation 27. TPS54334 C5_slvsc03.gif

To Maximize Phase margin, use Type-lll compensation to provide a zero around the desired crossover frequency (ƒco) with R5, VOUT and VREF.

Equation 28. TPS54334 Eq28_C8_SLUSC26.gif

For this design the calculated values for the compensation components are as follows:

R3 = 2.05 kΩ

C4 = 0.015 µF

C5 = 150 pF

C8 = 200 pF

8.2.1.2.7 Bootstrap Capacitor

Every TPS54334 design requires a bootstrap capacitor, C3. The bootstrap capacitor value must 0.1 μF. The bootstrap capacitor is located between the SW and BOOT pins. The bootstrap capacitor should be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

8.2.1.2.8 Power Dissipation Estimate

The following formulas show how to estimate the device power dissipation under continuous-conduction mode operations. These formulas should not be used if the device is working in the discontinuous conduction mode (DCM) or pulse-skipping Eco-mode™.

The device power dissipation includes:

  1. Conduction loss:
  2. Equation 29. PCON = IOUT2 × rDS(on) × VOUT / VIN

    where

    • IOUT is the output current (A)
    • rDS(on) is the on-resistance of the high-side MOSFET (Ω)
    • VOUT is the output voltage (V)
    • VIN is the input voltage (V)
  3. Switching loss:
  4. Equation 30. E = 0.5 × 10–9 × VIN 2 × IOUT × ƒSW

    where

    • ƒSW is the switching frequency (Hz)
  5. Gate charge loss:
  6. Equation 31. PG = 22.8 × 10–9 × ƒSW
  7. Quiescent current loss:
  8. Equation 32. PQ = 0.31 × 10-3 × VIN

Therefore:

Equation 33. Ptot = PCON + E + PG + PQ

where

  • Ptot is the total device power dissipation (W)

For given TA :

Equation 34. TJ = TA + Rth × Ptot

where

  • TA is the ambient temperature (°C)
  • TJ is the junction temperature (°C)
  • Rth is the thermal resistance of the package (°C/W)

For given TJmax = 150°C:

Equation 35. TAmax = TJmax – Rth × Ptot

where

  • TAmax is the maximum ambient temperature (°C)
  • TJmax is the maximum junction temperature (°C)

8.2.1.3 Application Curves

TPS54334 D017_SLUSC26.gif
Figure 20. TPS54334 Efficiency
TPS54334 D019_SLUSC26.gif
Figure 22. TPS54334 Load Regulation
TPS54334 D018_SLUSC26.gif
Figure 21. TPS54334 Low-Current Efficiency
TPS54334 D020_SLUSC26.gif
Figure 23. TPS54334 Line Regulation
TPS54334 trans_response_SLUSC26.gif
Time = 200 µs/div
0.75- to 2.25-A load step Slew rate = 500 mA/µs
Figure 24. TPS54334 Transient Response
TPS54334 fullload_out_ripple_SLUSC26.gif
Time = 1 µs/div
Figure 26. TPS54334 Full-Load Output Ripple
TPS54334 noload_out_ripple_SLUSC26.gif
Time = 2 ms/div
Figure 28. TPS54334 No-Load Output Ripple
TPS54334 startup_rel_to_VIN_SLUSC26.gif
Time = 2 ms/div
Figure 30. TPS54334 Startup Relative To VIN
TPS54334 shutdown_rel_to_VIN_SLUSC26.gif
Time = 2 ms/div
Figure 32. TPS54334 Shutdown Relative To VIN
TPS54334 D021_SLUSC26.gif
Figure 25. TPS54334 Loop Response
TPS54334 200mA_out_ripple_SLUSC26.gif
Time = 2 µs/div
Figure 27. TPS54334 200-mA Output Ripple
TPS54334 fullload_input_ripple_SLUSC26.gif
Time = 1 µs/div
Figure 29. TPS54334 Full-Load Input Ripple
TPS54334 startup_rel_to_EN_SLUSC26.gif
Time = 2 ms/div
Figure 31. TPS54334 Startup Relative To Enable
TPS54334 shutdown_rel_to_EN_SLUSC26.gif
Time = 2 ms/div
Figure 33. TPS54334 Shutdown Relative To EN