SLUSC26A May   2015  – February 2016 TPS54334

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Slope Compensation and Output Current
      4. 7.3.4  Bootstrap Voltage (BOOT) and Low Dropout Operation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Undervoltage Lockout
      9. 7.3.9  Slow Start
      10. 7.3.10 Safe Start-up into Pre-Biased Outputs
      11. 7.3.11 Power Good (PGOOD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overcurrent/Overvoltage/Thermal Protection
      2. 7.4.2 Thermal Shutdown
      3. 7.4.3 Small Signal Model for Loop Response
      4. 7.4.4 Small Signal Model for Peak Current Mode Control
      5. 7.4.5 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS54334 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Switching Frequency
          2. 8.2.1.2.2 Output Voltage Set Point
          3. 8.2.1.2.3 Undervoltage Lockout Set Point
          4. 8.2.1.2.4 Input Capacitors
          5. 8.2.1.2.5 Output Filter Components
            1. 8.2.1.2.5.1 Inductor Selection
            2. 8.2.1.2.5.2 Capacitor Selection
          6. 8.2.1.2.6 Compensation Components
          7. 8.2.1.2.7 Bootstrap Capacitor
          8. 8.2.1.2.8 Power Dissipation Estimate
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DRC Package
10 Pin VSON
Top View
TPS54334 DRC_pinout_SLUSC26.gif
DDA Package
8 Pin SO
Top View
TPS54334 DDA_pinout_SLUSC26.gif

Pin Functions

PIN NAME NUMBER I/O DESCRIPTION
DDA DRC
BOOT 1 9 O A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
COMP 6 7 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin.
EN 7 8 I Enable pin. Float to enable.
GND 4 3, 4, 5 – Ground.
PGOOD 8 10 O PGOOD open drain output. Connect a pull-up resistor with a value of 100kΩ to this pin.
SW 3 2 O The source of the internal high side power MOSFET.
Vin 2 1 – Input supply voltage, 4.2 V to 28 V.
VSENSE 5 6 I Inverting node of the gm error amplifier.
PowerPad (SO only) – GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance.
Thermal pad (VSON only)