JAJSP58 September   2022 TPS544C26

ADVANCE INFORMATION  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Programmable PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Differential Remote Sense and Internal Feedback Divider
      4. 7.3.4  Set the Output Voltage and VID Table
      5. 7.3.5  Startup and Shutdown
      6. 7.3.6  Dynamic Voltage Slew Rate
      7. 7.3.7  Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
      8. 7.3.8  Loop Compensation
      9. 7.3.9  Set Switching Frequency
      10. 7.3.10 Switching Node (SW)
      11. 7.3.11 Overcurrent Limit and Low-side Current Sense
      12. 7.3.12 Negative Overcurrent Limit
      13. 7.3.13 Zero-Crossing Detection
      14. 7.3.14 Input Overvoltage Protection
      15. 7.3.15 Output Overvoltage and Undervoltage Protection
      16. 7.3.16 Overtemperature Protection
      17. 7.3.17 VR Ready
      18. 7.3.18 Catastrophic Fault Alert: CAT_FAULT#
      19. 7.3.19 Telemetry
      20. 7.3.20 I2C Interface General Description
        1. 7.3.20.1 Setting the I2C Address
        2. 7.3.20.2 I2C Write Protection
        3. 7.3.20.3 I2C Registers With Special Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
    5. 7.5 Programming
      1. 7.5.1 Supported I2C Registers
      2. 7.5.2 Support of Intel SVID Interface
    6. 7.6 Register Maps
      1. 7.6.1  (01h) OPERATION
      2. 7.6.2  (02h) ON_OFF_CONFIG
      3. 7.6.3  (03h) CLEAR_FAULTS
      4. 7.6.4  (15h) STORE_USER_ALL
      5. 7.6.5  (16h) RESTORE_USER_ALL
      6. 7.6.6  (33h) FREQUENCY_SWITCH
      7. 7.6.7  (35h) VIN_ON
      8. 7.6.8  (36h) VIN_OFF
      9. 7.6.9  (40h) VOUT_OV_FAULT_LIMIT
      10. 7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.6.11 (42h) VOUT_OV_WARN_LIMIT
      12. 7.6.12 (43h) VOUT_UV_WARN_LIMIT
      13. 7.6.13 (44h) VOUT_UV_FAULT_LIMIT
      14. 7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
      15. 7.6.15 (46h) IOUT_OC_FAULT_LIMIT
      16. 7.6.16 (4Fh) OT_FAULT_LIMIT
      17. 7.6.17 (50h) OT_FAULT_RESPONSE
      18. 7.6.18 (51h) OT_WARN_LIMIT
      19. 7.6.19 (55h) VIN_OV_FAULT_LIMIT
      20. 7.6.20 (60h) TON_DELAY
      21. 7.6.21 (61h) TON_RISE
      22. 7.6.22 (64h) TOFF_DELAY
      23. 7.6.23 (65h) TOFF_FALL
      24. 7.6.24 (6Bh) PIN_OP_WARN_LIMIT
      25. 7.6.25 (7Ah) STATUS_VOUT
      26. 7.6.26 (7Bh) STATUS_IOUT
      27. 7.6.27 (7Ch) STATUS_INPUT
      28. 7.6.28 (7Dh) STATUS_TEMPERATURE
      29. 7.6.29 (80h) STATUS_MFR_SPECIFIC
      30. 7.6.30 (88h) READ_VIN
      31. 7.6.31 (89h) READ_IIN
      32. 7.6.32 (8Bh) READ_VOUT
      33. 7.6.33 (8Ch) READ_IOUT
      34. 7.6.34 (8Dh) READ_TEMPERATURE_1
      35. 7.6.35 (97h) READ_PIN
      36. 7.6.36 (A0h) SYS_CFG_USER1
      37. 7.6.37 (A2h) I2C_ADDR
      38. 7.6.38 (A3h) SVID_ADDR
      39. 7.6.39 (A4h) IMON_CAL
      40. 7.6.40 (A5h) IIN_CAL
      41. 7.6.41 (A6h) VOUT_CMD
      42. 7.6.42 (A7h) VID_SETTING
      43. 7.6.43 (A8h) I2C_OFFSET
      44. 7.6.44 (A9h) COMP1_MAIN
      45. 7.6.45 (AAh) COMP2_MAIN
      46. 7.6.46 (ABh) COMP1_ALT
      47. 7.6.47 (ACh) COMP2_ALT
      48. 7.6.48 (ADh) COMP3
      49. 7.6.49 (AFh) DVS_CFG
      50. 7.6.50 (B0h) DVID_OFFSET
      51. 7.6.51 (B1h) REG_LOCK
      52. 7.6.52 (B3h) PIN_SENSE_RES
      53. 7.6.53 (B4h) IOUT_NOC_LIMIT
      54. 7.6.54 (B5h) USER_DATA_01
      55. 7.6.55 (B6h) USER_DATA_02
      56. 7.6.56 (BAh) STATUS1_SVID
      57. 7.6.57 (BBh) STATUS2_SVID
      58. 7.6.58 (BCh) CAPABILITY
      59. 7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
      60. 7.6.60 (BEh) VIDOMAX_L
      61. 7.6.61 (C0h) ICC_MAX
      62. 7.6.62 (C1h) TEMP_MAX
      63. 7.6.63 (C2h) PROTOCOL_ID_SVID
      64. 7.6.64 (C6h) VENDOR_ID
      65. 7.6.65 (C8h) PRODUCT_ID
      66. 7.6.66 (C9h) PRODUCT_REV_ID
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 VINSENP and VINSENN Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 I2C Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS544C26EVM
  9. Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

(C2h) PROTOCOL_ID_SVID

CMD Address C2h
Write Transaction: Write Byte
Read Transaction: Read Byte
Format: Unsigned Binary (1 byte)
NVM Back-up: EEPROM
Updates:

Vboot: on-the-fly.

PROTOCOL_ID and ALL_CALL_SEL: field value update will wait until the power conversion is disabled.

This PROTOCOL_ID_SVID command contains 3 fields for configuring the SVID Protocol ID, Vboot (boot up voltage), and All-call address selection.

The PROTOCOL_ID bits set the Protocol ID for SVID communication. The setting also programs an internal precision resistor divider thus determines the VOUT scaling (mV/LSB) of the device.

The Vboot bits program the initial output voltage at start-up when the output voltage is controlled by SVID interface (e.g. VOUT_CTRL = 00b or 01b).

The ALL_CALL_SEL bits set the All-call address for SVID communication.

Return to Supported I2C and Default Values.

Figure 7-64 (C2h) PROTOCOL_ID_SVID Register Map
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
PROTOCOL_ID Vboot ALL_CALL_SEL
LEGEND: R/W = Read/Write; R = Read only
Table 7-85 Register Field Descriptions
Bit Field Access Reset Description
7:6 PROTOCOL_ID R/W NVM These bits set the Protocol ID for SVID communication. The setting also programs an internal precision resistor divider thus determines the VOUT scaling (mV/LSB) of the device.

00b: SVID PROTOCOL ID = 04h (VR13, 10 mV). And VOUT_CMD step = 10 mV/LSB

01b: SVID PROTOCOL ID = 07h (VR13, 5 mV). And VOUT_CMD step = 5 mV/LSB

10b: SVID PROTOCOL ID = 09h (VR14, 5 mV). And VOUT_CMD step = 5 mV/LSB

11b: SVID PROTOCOL ID = 0Ah (VR14, 10 mV). And VOUT_CMD step = 10 mV/LSB

The function selected in this field is loaded into SVID register (05h) PROTOCOL_ID as well. In order for this field to take effect, the power conversion must be disabled.

Note: The TPS544C26 device is VR13 compliant and no support to VR14.

5:2 Vboot R/W NVM These bits program the initial output voltage at start-up. See Table 7-86 for the available settings. The Vboot and Protocol ID selections have to align based on the listed options on Table 7-86 no matter the VOUT adjustment is controlled by SVID interface or I2C interface. Otherwise, an error check will NACK the write attempt. For example, a write attempt with C2h = 011111xxb (Vboot = 1.8 V and Protocol ID = 5 mV) will be NACKed, while a write attempt with C2h = 011000xxb (Vboot = 1.1V and Protocol ID = 5mV) will be ACKed.

The function selected in this field is loaded into SVID register (26h) VBOOT as well, in VID format.

1:0 ALL_CALL_SEL R/W NVM These bits set the All-call address for SVID communication.

00b: Not support All-call address, will reject both 0Eh and 0Fh address

01b: Respond to All-call address 0Fh only

10b: Respond to All-call address 0Eh only

11b: Respond to All-call address both 0Eh and 0Fh

The function selected in this field is loaded into SVID register (0Fh) ALLCALL_ACT as well. In order for this field to take effect, the power conversion must be disabled.

Table 7-86 Vboot settings
Vboot VID code(1) (Hex) Vboot (V) PROTOCOL_ID
0000b 00h 0 Must set PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV)
0001b 65h 0.75
0010b 6Fh 0.80
0011b 79h 0.85
0100b 83h 0.90
0101b 8Dh 0.95
0110b 97h 1.00
0111b A1h 1.05
1000b ABh 1.10
1001b AFh 1.20
1010b C9h 1.25
1011b DDh 1.35
1100b FBh 1.50
1101b 6Fh 1.60 Must set PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV)
1110b 79h 1.70
1111b 83h 1.80
VID code is not directly visiable to customer but shows up in I2C register (A7h) VID_SETTING and SVID register (31h) VID_SETTING.