JAJSLY1G July   2013  – June 2021 TPS54561

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft Start/Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      11. 7.3.11 Maximum Switching Frequency
      12. 7.3.12 Synchronization to RT/CLK Pin
      13. 7.3.13 Accurate Current Limit Operation
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Output Inductor Selection (LO)
          4. 8.2.1.2.4  Output Capacitor
          5. 8.2.1.2.5  Catch Diode
          6. 8.2.1.2.6  Input Capacitor
          7. 8.2.1.2.7  Slow Start Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor Selection
          9. 8.2.1.2.9  Undervoltage Lockout Set Point
          10. 8.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 8.2.1.2.11 Compensation
          12. 8.2.1.2.12 Power Dissipation Estimate
          13. 8.2.1.2.13 Safe Operating Area
          14. 8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output
      3. 8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design with WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Small Signal Model for Frequency Compensation

The TPS54561 uses a transconductance amplifier for the error amplifier and supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 7-19. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small signal model in Figure 7-19. The open-loop gain and bandwidth are modeled using the RO and CO shown in Figure 7-19. See the application section for a design example using a Type 2A network with a low ESR output capacitor.

Equation 18 through Equation 27 are provided as a reference. An alternative is to use WEBENCH software tools to create a design based on the power supply requirements.

GUID-AB691CC4-E54F-41A1-A395-E67FC1B5C69F-low.gifFigure 7-19 Types of Frequency Compensation
GUID-9793BE98-47E7-4C0F-932B-E912694A15C1-low.gifFigure 7-20 Frequency Response of the Type 2A and Type 2B Frequency Compensation
Equation 18. GUID-1D1DF621-B2EC-4A5F-B4CC-8620863485C4-low.gif
Equation 19. GUID-ED33D637-F032-4B9D-A244-F92CFBA38C79-low.gif
Equation 20. GUID-8D6FD41F-4938-4525-B251-2D4B23D2514C-low.gif
Equation 21. GUID-1D3AE7A1-5919-4739-8284-63DDB4F07287-low.gif
Equation 22. GUID-4E0D06F2-30E5-45C5-B465-5E1B9E8665E0-low.gif
Equation 23. GUID-3586B66C-50C5-42AB-AD20-7C9D85175B70-low.gif
Equation 24. GUID-3F9FE646-D902-4ACF-93BF-49F010C0A31D-low.gif
Equation 25. GUID-6D495772-567B-4B83-A7B9-6E1733AD6460-low.gif
Equation 26. GUID-EDF38562-7B81-4FDA-9B58-78BE37964382-low.gif
Equation 27. GUID-9690B228-F82D-4691-87B5-9C5B4262C575-low.gif