JAJSBM7C September   2011  – October 2017 TPS54623

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     効率と負荷電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-up into Pre-Biased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Slope Compensation
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Slow Start (SS/TR)
      9. 7.3.9  Power Good (PWRGD)
      10. 7.3.10 Bootstrap Voltage (BOOT) and Low Dropout Operation
      11. 7.3.11 Sequencing (SS/TR)
      12. 7.3.12 Output Overvoltage Protection (OVP)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 High-side MOSFET Overcurrent Protection
        2. 7.3.13.2 Low-side MOSFET Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Small Signal Model for Loop Response
      16. 7.3.16 Simple Small Signal Model for Peak Current Mode Control
      17. 7.3.17 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed Frequency PWM Control
      2. 7.4.2 Continuous Current Mode Operation (CCM)
      3. 7.4.3 Light Load Efficiency Operation
      4. 7.4.4 Adjustable Switching Frequency and Synchronization (RT/CLK)
        1. 7.4.4.1 Adjustable Switching Frequency (RT Mode)
        2. 7.4.4.2 Synchronization (CLK mode)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Fast Transient Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Under Voltage Lockout Set Point
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Estimated Circuit Area
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
      3. 11.1.3 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.10 Compensation Component Selection

There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54623. Since the slope compensation is ignored, the actual crossover frequency is usually lower than the cross over frequency used in the calculations.

First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 31 and Equation 32. For Cout, use a derated value of 75 µF. use Equation 33 and Equation 34 to estimate a starting point for the closed loop crossover frequency fco. Then the required compensation components may be derived. For this design example, fpmod is 3.86 kHz and fzmod is 707.4 kHz. Equation 33 is the geometric mean of the modulator pole and the esr zero and Equation 34 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this case Equation 33 yields 52.2 kHz and Equation 34 yields 30.4 kHz. The lower value is 30.4 kHz. A slightly higher frequency of 30 kHz is chosen as the intended crossover frequency.

Equation 31. TPS54623 eq28_fpmod_lvs949.gif
Equation 32. TPS54623 eq29_fzmod_lvs949.gif
Equation 33. TPS54623 eq30_fco1_lvs949.gif
Equation 34. TPS54623 eq31_fco2_lvs949.gif

Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the compensated network at the crossover frequency. Use Equation 35 to determine the value of R2.

Equation 35. TPS54623 eq35_r4_lvsa70.gif

Next calculate the value of C3. Together with R2, C3 places a compensation zero at the modulator pole frequency. Equation 36 to determine the value of C3.

Equation 36. TPS54623 eq36_c4_lvsa70.gif

Using Equation 35 and Equation 36 the standard values for R4 and C4 are 3.74 kΩ and 0.01 µF.

An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R4 and C4. The pole frequency can be placed at the ESR zero frequency of the output capacitor as given by Equation 12. Use Equation 37 to calculate the required capacitor value for C5.

Equation 37. TPS54623 eq37_c5_lvsa70.gif