JAJSDE0A June   2017  – February 2024 TPS549B22

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 25-A FET
      2. 6.3.2 On-Resistance
      3. 6.3.3 Package Size, Efficiency and Thermal Performance
      4. 6.3.4 Soft-Start Operation
      5. 6.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 6.3.6 EN_UVLO Pin Functionality
      7. 6.3.7 Fault Protections
        1. 6.3.7.1 Current Limit (ILIM) Functionality
        2. 6.3.7.2 VDD Undervoltage Lockout (UVLO)
        3. 6.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        4. 6.3.7.4 Out-of-Bounds Operation
        5. 6.3.7.5 Overtemperature Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 D-CAP3™ Control Mode Topology
      2. 6.4.2 DCAP Control Topology
    5. 6.5 Programming
      1. 6.5.1 Programmable Pin-Strap Settings
        1. 6.5.1.1 Address Selection (ADDR) Pin
        2. 6.5.1.2 VSEL Pin
        3. 6.5.1.3 D-CAP3™ Control Mode Selection
        4. 6.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 6.5.2 Programmable Analog Configurations
        1. 6.5.2.1 RSP/RSN Remote Sensing Functionality
          1. 6.5.2.1.1 Output Differential Remote Sensing Amplifier
        2. 6.5.2.2 Power Good (PGOOD Pin) Functionality
      3. 6.5.3 PMBus Programming
        1. 6.5.3.1 TPS549B22 Limitations to the PMBUS Specifications
        2. 6.5.3.2 Target Address Assignment
        3. 6.5.3.3 PMBUS Address Selection
        4. 6.5.3.4 Supported Formats
          1. 6.5.3.4.1 Direct Format — Write
          2. 6.5.3.4.2 Combined Format — Read
        5. 6.5.3.5 Stop Separated Reads
        6. 6.5.3.6 Supported PMBUS Commands and Registers
  8. Register Maps
    1. 7.1  OPERATION Register (address = 1h)
    2. 7.2  ON_OFF_CONFIG Register (address = 2h)
    3. 7.3  CLEAR FAULTS (address = 3h)
    4. 7.4  WRITE PROTECT (address = 10h)
    5. 7.5  STORE_DEFAULT_ALL (address = 11h)
    6. 7.6  RESTORE_DEFAULT_ALL (address = 12h)
    7. 7.7  CAPABILITY (address = 19h)
    8. 7.8  VOUT_MODE (address = 20h)
    9. 7.9  VOUT_COMMAND (address = 21h)
    10. 7.10 VOUT_MARGIN_HIGH (address = 25h) ®
    11. 7.11 VOUT_MARGIN_LOW (address = 26h)
    12. 7.12 STATUS_BYTE (address = 78h)
    13. 7.13 STATUS_WORD (High Byte) (address = 79h)
    14. 7.14 STATUS_VOUT (address = 7Ah)
    15. 7.15 STATUS_IOUT (address = 7Bh)
    16. 7.16 STATUS_CML (address = 7Eh)
    17. 7.17 MFR_SPECIFIC_00 (address = D0h)
    18. 7.18 MFR_SPECIFIC_01 (address = D1h)
    19. 7.19 MFR_SPECIFIC_02 (address = D2h)
    20. 7.20 MFR_SPECIFIC_03 (address = D3h)
    21. 7.21 MFR_SPECIFIC_04 (address = D4h)
    22. 7.22 MFR_SPECIFIC_06 (address = D6h)
    23. 7.23 MFR_SPECIFIC_07 (address = D7h)
    24. 7.24 MFR_SPECIFIC_44 (address = FCh)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS549B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1  Custom Design With WEBENCH® Tools
        2. 8.2.3.2  Switching Frequency Selection
        3. 8.2.3.3  Inductor Selection
        4. 8.2.3.4  Output Capacitor Selection
          1. 8.2.3.4.1 Minimum Output Capacitance to Make Sure of Stability
          2. 8.2.3.4.2 Response to a Load Transient
          3. 8.2.3.4.3 Output Voltage Ripple
        5. 8.2.3.5  Input Capacitor Selection
        6. 8.2.3.6  Bootstrap Capacitor Selection
        7. 8.2.3.7  BP Pin
        8. 8.2.3.8  R-C Snubber and VIN Pin High-Frequency Bypass
        9. 8.2.3.9  Optimize Reference Voltage (VSEL)
        10. 8.2.3.10 MODE Pin Selection
        11. 8.2.3.11 ADDR Pin Selection
        12. 8.2.3.12 Overcurrent Limit Design
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
      3. 8.4.3 Mounting and Thermal Profile Recommendation
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ(パッケージ|ピン)
  • RVF|40
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETERTEST CONDITIONMINTYPMAXUNIT
MOSFET ON-RESISTANCE (RDS(on))
RDS(on)High-side FET(VBOOT – VSW) = 5 V, ID = 25 A, TJ = 25°C4.1
Low-side FETVVDD = 5 V, ID = 25 A, TJ = 25°C1.9
INPUT SUPPLY AND CURRENT
VVDDVDD supply voltageNominal VDD voltage range4.522V
IVDDVDD bias currentNo load, power conversion enabled (no switching), TA = 25°C,2mA
IVDDSTBYVDD standby currentNo load, power conversion disabled, TA = 25°C700µA
UNDERVOLTAGE LOCKOUT
VVDD_UVLOVDD UVLO rising threshold4.1234.254.41V
VVDD_UVLO(HYS)VDD UVLO hysteresis0.2V
VEN_ON_THEN_UVLO on threshold1.451.61.75V
VEN_HYSEN_UVLO hysteresis270300340mV
IEN_LKGEN_UVLO input leakage currentVEN_UVLO = 5 V–101µA
INTERNAL REFERENCE VOLTAGE RANGE
VINTREFInternal REF voltage900.4mV
VINTREFTOLInternal REF voltage tolerance–40°C ≤ TJ ≤ 125°C–0.5%0.5%
VINTREFInternal REF voltage range0.61.2V
OUTPUT VOLTAGE
VIOS_LPCMPLoop comparator input offset voltage(1)–2.52.5mV
IRSPRSP input currentVRSP = 600 mV–11µA
IVO(dis)VO discharge currentVVO = 0.5 V, power conversion disabled812mA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
fUGBWUnity gain bandwidth(1)57MHz
A0Open loop gain(1)75dB
SRSlew rate(1)±4.7V/µsec
VIRNGInput range(1)–0.21.8V
VOFFSETInput offset voltage(1)–3.53.5mV
INTERNAL BOOT STRAP SWITCH
VFForward voltageVBP-BOOT, IF = 10 mA, TA = 25°C0.10.2V
IBOOTVBST leakage currentVBOOT = 30 V, VSW = 25 V, TA = 25°C0.011.5µA
SWITCHING FREQUENCY
fSWVO switching frequency(2)VIN = 12 V, VVO = 1 V, TA = 25°C275315350kHz
380425475
490550615
585650740
740825930
790900995
92010251160
95011251250
tON(min)Minimum on-time(1)60ns
tOFF(min)Minimum off-time(1)DRVH falling to rising300ns
MODE, VSEL, ADDR DETECTION
VDETECT_THMODE, VSEL, and ADDR detection voltageVBP = 2.93 V,
RHIGH = 100 kΩ
OpenVBPV
RLOW = 187 kΩ1.9091
RLOW = 165 kΩ1.8243
RLOW = 147 kΩ1.7438
RLOW = 133 kΩ1.6725
RLOW = 121 kΩ1.6042
RLOW = 110 kΩ1.5348
RLOW = 100 kΩ1.465
RLOW = 90.9 kΩ1.3952
RLOW = 82.5 kΩ1.3245
RLOW = 75 kΩ1.2557
RLOW = 68.1 kΩ1.187
RLOW = 60.4 kΩ1.1033
RLOW = 53.6 kΩ1.0224
RLOW = 47.5 kΩ0.9436
RLOW = 42.2 kΩ0.8695
RLOW = 37.4 kΩ0.7975
RLOW = 33.2 kΩ0.7303
RLOW = 29.4 kΩ0.6657
RLOW = 25.5 kΩ0.5953
RLOW = 22.1 kΩ0.5303
RLOW = 19.1 kΩ0.4699
RLOW = 16.5 kΩ0.415
RLOW = 14.3 kΩ0.3666
RLOW = 12.1 kΩ0.3163
RLOW = 10 kΩ0.2664
RLOW = 7.87 kΩ0.2138
RLOW = 6.19 kΩ0.1708
RLOW = 4.64 kΩ0.1299
RLOW = 3.16 kΩ0.0898
RLOW = 1.78 kΩ0.0512
RLOW = 0 ΩGND
SOFT-START
tSSSoft-start timeVOUT rising from 0 V to 95% of final set point, RMODE_HIGH = 100 kΩRMODE_LOW = 60.4 kΩ78(4)10ms
RMODE_LOW = 53.6 kΩ3.64(5)5.2
RMODE_LOW = 47.5 kΩ1.622.8
RMODE_LOW = 42.2 kΩ0.811.6
POWER-ON DELAY
tPODLYPower-on delay timeDelay from enable to switching POD[2:0] = 000256µs
Delay from enable to switching POD[2:0] = 001512
Delay from enable to switching POD[2:0] = 0101.024ms
Delay from enable to switching POD[2:0] = 0112.048
Delay from enable to switching POD[2:0] = 1004.096
Delay from enable to switching POD[2:0] = 1018.192
Delay from enable to switching POD[2:0] = 11016.384
Delay from enable to switching POD[2:0] = 11132.768
PGOOD COMPARATOR
VPGTHPGOOD thresholdPGOOD in from higher105108111%VREF
PGOOD in from lower899295
PGOOD out to higher120
PGOOD out to lower68
IPGPGOOD sink currentVPGOOD = 0.5 V6.9mA
tPGDLYPGOOD delay timeDelay for PGOOD going in, PGD[2:0] = 000256µs
Delay for PGOOD going in, PGD[2:0] = 001512
Delay for PGOOD going in, PGD[2:0] = 0101.024ms
Delay for PGOOD going in, PGD[2:0] = 0112.048
Delay for PGOOD going in, PGD[2:0] = 1004.096
Delay for PGOOD going in, PGD[2:0] = 1018.192
Delay for PGOOD going in, PGD[2:0] = 11016.384
Delay for PGOOD going in, PGD[2:0] = 111131
Delay for PGOOD coming out2µs
IPGLKPGOOD leakage currentVPGOOD = 5 V–101μA
CURRENT DETECTION
IOCL_VAValley current limit thresholdRLIM = 61.9 kΩ30A
OC tolerance±15%(3)
RLIM = 51.1 kΩ25A
OC tolerance±15%(3)
RLIM = 40.2 kΩ172023A
IOCL_VA_NNegative valley current limit thresholdRLIM = 61.9 kΩ–30A
RLIM = 51.1 kΩ–25
RLIM = 40.2 kΩ–20
ICLMP_LOClamp current at VLIM clamp at lowestVILIM_CLMP = 0.1 V, TA = 25°C5A
ICLMP_HIClamp current at VLIM clamp at highestVILIM_CLMP = 1.2 V, TA = 25°C50A
PROTECTIONS AND OOB
VBPUVLOBP UVLO threshold voltageWake-up3.32V
Shutdown3.11
VOVPOVP threshold voltageOVP detect voltage117%120%123%VREF
tOVPDLYOVP response time100-mV over drive1µs
VUVPUVP threshold voltageUVP detect voltage65%68%71%VREF
tUVPDLYUVP delay filter delay time1ms
VOOBOOB threshold voltage8%VREF
tHICDLYHiccup blanking timetSS = 1 ms16ms
tSS = 2 ms24ms
tSS = 4 ms38ms
tSS = 8 ms67ms
BP VOLTAGE
VBPBP LDO output voltageVIN = 12 V, 0 A ≤ ILOAD ≤ 10 mA,5.07V
VBPDOBP LDO dropout voltageVIN = 4.5 V, ILOAD = 30 mA, TA = 25°C365mV
IBPMAXBP LDO overcurrent limitVIN = 12 V, TA = 25°C100mA
PMB_CLK and PMB_DATA INPUT BUFFER LOGIC THRESHOLDS
VIL-PMBUSPMB_CLK and PMB_DATA low-level input voltage(1)0.8V
VIH-PMBUSPMB_CLK and PMB_DATA high-level input voltage(1)1.35V
VHY-PMBUSPMB_CLK and PMB_DATA hysteresis voltage(1)150mV
PMB_CLK and SMB_ALRT OUTPUT PULLDOWN
VOL-PMBUSPMB_DATA and SMB_ALRT low-level output voltage(1)ISINK = 20 mA0.4V
THERMAL SHUTDOWN
TSDNBuilt-In thermal shutdown threshold(1)Shutdown temperature155165°C
Hysteresis30
Specified by design. Not production tested.
Correlated with close-loop EVM measurement at load current of 30 A.
Calculated from 20-A test data. Not production tested.
To use the 8-ms SS setting, follow the steps outlined in Section 6.5.1.4.
To use the 4-ms SS setting, follow the steps outlined in Section 6.5.1.4.