JAJSEW8E February   2017  – August 2019 TPS61178

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Under-voltage Lockout
      2. 8.3.2  Enable and Disable
      3. 8.3.3  Startup
      4. 8.3.4  Load Disconnect Gate Driver
      5. 8.3.5  Adjustable Peak Current Limit
      6. 8.3.6  Output Short Protection (with load disconnected FET)
      7. 8.3.7  Adjustable Switching Frequency
      8. 8.3.8  External Clock Synchronization (TPS611781)
      9. 8.3.9  Error Amplifier
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Start-up with the Output Pre-Biased
      12. 8.3.12 Bootstrap Voltage (BST)
      13. 8.3.13 Over-voltage Protection
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation
      2. 8.4.2 Auto PFM Mode (TPS61178)
      3. 8.4.3 Forced PWM Mode (TPS611781)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting the Switching Frequency
      3. 9.2.3 Setting the Current Limit
      4. 9.2.4 Setting the Output Voltage
        1. 9.2.4.1 Selecting the Inductor
        2. 9.2.4.2 Selecting the Output Capacitors
        3. 9.2.4.3 Selecting the Input Capacitors
        4. 9.2.4.4 Loop Stability and Compensation
          1. 9.2.4.4.1 Small Signal Model
          2. 9.2.4.4.2 Loop Compensation Design Steps
          3. 9.2.4.4.3 Selecting the Disconnect FET
          4. 9.2.4.4.4 Selecting the Bootstrap Capacitor
          5. 9.2.4.4.5 VCC Capacitor
      5. 9.2.5 TPS61178 Application Waveform
    3. 9.3 System Examples
      1. 9.3.1 TPS61178 with 14-V Output from 2.7-V to 4.4-V Input Voltage
      2. 9.3.2 TPS61178 Without Load Disconnect Function
      3. 9.3.3 TPS611781 External Clock Synchronization
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values are at TJ = 25°C, (unless otherwise noted)
MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 2.7 20 V
VIN_UVLO Input voltage under voltage lockout (UVLO) threshold VIN rising 2.6 2.7 V
VIN falling 2.2 2.3
VIN_HYS VIN UVLO hysteresis 400 mV
VCC VCC regulation voltage ICC = 5mA, VIN = 8V 6 V
VCC_UVLO VCC UVLO threshold VCC falling 2.1 V
IQ (TPS61178) Quiescent current into VIN pin IC enabled, no load, no ext. FET



VIN =  6 V, VOUT = 20 V, VFB = 1.3 V, TJ up to 85 ⁰C		 1.5 3 µA
Quiescent current into VIN pin IC enabled, no load, no ext. FET


VIN = 20 V, VOUT = 20 V, VFB = 1.3 V,TJ up to 85 ⁰C		 270 320 µA
Quiescent current into VOUT pin IC enabled, no load, no ext. FET





VIN = 6 V, VFB = 1.3 V, VOUT = 20 V, TJ up to 85 ⁰C		 250 300 µA
Quiescent current into VOUT pin IC enabled, no load, no ext. FET



VIN = 20 V, VOUT = 20 V, VFB = 1.3 V, TJ up to 85 ⁰C		 5 12 µA
ISD Shutdown current into VIN pin IC disabled, VIN = 6 V,

–40 °C ≤ TJ ≤ 85°C		 1 3.5 µA
IC disabled, VIN =  20 V,

–40 °C ≤ TJ ≤ 85°C		 3 6 µA
ILS_LKG Reverse leakage current into SW IC disabled, VIN = VOUT = SW = 20 V

–40 °C ≤ TJ ≤ 85°C		 0.1 6.5 µA
OUTPUT
VOLTAGE
VOUT Output voltage range Freq = 500kHz 4.5 20 V
VOVP Output over-voltage protection threshold VIN  = 8 V, VOUT rising 20.5 21 21.5 V
POWER
SWITCHES
RDS(on) High-side MOSFET on resistance VCC = 6 V 16 25 mΩ
Low-side MOSFET on resistance VCC = 6 V 16 25 mΩ
Gm Power stage trans-conductance
(peak current ratio with comp voltage)		 VCC = 6 V 12 A/V
CURRENT
LIMIT
ILIM_SW TPS61178  RLIMIT = 80.6 kΩ 6.4 8 9.4 A
ILIM_SW TPS611781 RLIMIT = 80.6 kΩ 5.7 7.4 8.7 A
ILIM_SHORT TPS61178 short current limit 20 A
VOLTAGE
REFERNCE
VREF Reference Voltage at FB pin PWM mode 1.180 1.198 1.210 V
PFM mode 101% VREF
IFB_LKG Leakage current into FB pin 10 60 nA
EN / SYNC LOGIC
VEN_H EN Logic high threshold 1.2 V
VEN_L EN Logic Low threshold 0.4 V
REN EN pulldown resistor 800 kΩ
VSYNC_H SYNC clock high threshold 1.2 V
VSYNC_L SYNC clock low threshold 0.4 V
ERROR
AMPLIFIER
VCOMPH COMP output high voltage High threshold, VFB = VREF - 200 mV 1.9 V
VCOMPL COMP output low voltage Low threshold, VFB = VREF + 200 mV 1.25 V
GmEA Error amplifier trans conductance VCOMP = 1.5 V 195 uS
ISINK Comp pin sink current VFB = VREF + 200 mV, VCOMP = 1.5 V 20 uA
ISOURCE Comp pin source current VFB = VREF –200 mV, VCOMP = 1.5 V 20 uA