JAJSEW8E February   2017  – August 2019 TPS61178

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Under-voltage Lockout
      2. 8.3.2  Enable and Disable
      3. 8.3.3  Startup
      4. 8.3.4  Load Disconnect Gate Driver
      5. 8.3.5  Adjustable Peak Current Limit
      6. 8.3.6  Output Short Protection (with load disconnected FET)
      7. 8.3.7  Adjustable Switching Frequency
      8. 8.3.8  External Clock Synchronization (TPS611781)
      9. 8.3.9  Error Amplifier
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Start-up with the Output Pre-Biased
      12. 8.3.12 Bootstrap Voltage (BST)
      13. 8.3.13 Over-voltage Protection
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation
      2. 8.4.2 Auto PFM Mode (TPS61178)
      3. 8.4.3 Forced PWM Mode (TPS611781)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting the Switching Frequency
      3. 9.2.3 Setting the Current Limit
      4. 9.2.4 Setting the Output Voltage
        1. 9.2.4.1 Selecting the Inductor
        2. 9.2.4.2 Selecting the Output Capacitors
        3. 9.2.4.3 Selecting the Input Capacitors
        4. 9.2.4.4 Loop Stability and Compensation
          1. 9.2.4.4.1 Small Signal Model
          2. 9.2.4.4.2 Loop Compensation Design Steps
          3. 9.2.4.4.3 Selecting the Disconnect FET
          4. 9.2.4.4.4 Selecting the Bootstrap Capacitor
          5. 9.2.4.4.5 VCC Capacitor
      5. 9.2.5 TPS61178 Application Waveform
    3. 9.3 System Examples
      1. 9.3.1 TPS61178 with 14-V Output from 2.7-V to 4.4-V Input Voltage
      2. 9.3.2 TPS61178 Without Load Disconnect Function
      3. 9.3.3 TPS611781 External Clock Synchronization
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Startup

When the input voltage to the device exceeds the UVLO threshold and EN pin pulled to high as well, the TPS61178x starts to ramp up the output voltage. There is a switching pre-charge phase and the output voltage is charged up to 10% higher than the input voltage (1.1 x VIN). The switching frequency is a fixed 500 kHz at the pre-charge phase.

After the pre-charge phase ends (typical 2.6 ms), The TPS61178x regulates the FB pin to the internal soft start voltage and results in a gradual rise of the output voltage starting from the input voltage level to the target output voltage. The soft start time is typical 3.2 ms, which helps the regulator to gradually reach the steady state setting point, thus reducing the startup stresses and surges. The switching frequency follows the oscillator setting by the resistor connecting with the FREQ / SYNC pin.

If the device is synchronized by the external clock, the switching frequency is fixed 500 kHz at the soft start phase and changes to the external clock when the soft start phase ends.