SLVS952G April   2010  – January 2017 TPS62671 , TPS62672 , TPS62674 , TPS62675 , TPS626751 , TPS626765 , TPS62679

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Switching Frequency
      2. 10.3.2 Power Save Mode
      3. 10.3.3 Mode Selection
      4. 10.3.4 Spread Spectrum, PWM Frequency Dithering
      5. 10.3.5 Short-Circuit Protection
      6. 10.3.6 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Soft Start
      2. 10.4.2 Enable
      3. 10.4.3 Active Output Discharge
      4. 10.4.4 Undervoltage Lockout
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 TPS6267x Point-Of-Load Supply
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Inductor Selection
          2. 11.2.1.2.2 Output Capacitor Selection
          3. 11.2.1.2.3 Input Capacitor Selection
          4. 11.2.1.2.4 Checking Loop Stability
        3. 11.2.1.3 Application Curves
      2. 11.2.2 1.26V CMOS Sensor Embedded Power Solution — Featuring Sub 0.4mm Profile
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
        1. 14.2.1.1 References
    3. 14.3 Related Links
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout

Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. High-speed operation of the TPS6267x devices demand careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths.

The ground pins of the dc/dc converter must be strongly connected to the PCB ground (i.e. reference potential across the system). These ground pins serve as the return path for both the control circuitry and the synchronous rectifier. Furthermore, due to its high frequency switching circuitry, it is imperative for the input capacitor to be as close to the SMPS device as possible, and that there is an unbroken ground plane under the TPS6267x and its external passives. Additionally, minimizing the area between the SW pin trace and inductor will limit high frequency radiated energy. The feed-back line should be routed away from noisy components and traces (e.g. SW line).

The output capacitor carries the inductor ripple current. While not as critical as the input capacitor, an unbroken ground connection from this capacitor’s ground return to the inductor, input capacitor and SMPS device will reduce the output voltage ripple and it’s associated ESL step. This is a critical aspect to achieve best loop and frequency stability.

High frequency currents tend to find their way on the ground plane along a mirror path directly beneath the incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There should be a group of vias in the surrounding of the dc/dc converter leading directly down to an internal ground plane. To minimize parasitic inductance, the ground plane should be as close as possible to the top plane of the PCB (i.e. onto which the components are located).

Layout Example

TPS62671 TPS62672 TPS62674 TPS62675 TPS626751 TPS626765 TPS62679 layout_lvs952.gif Figure 53. Suggested Layout (Top)