JAJSQ70D january   2014  – may 2023 TPS65262

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting Undervoltage Lockout
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
        1. 7.3.4.1 External Power Sequencing
        2. 7.3.4.2 Automatic Power Sequencing
      5. 7.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  PSM
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Overcurrent Protection
        1. 7.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 7.3.11 Power Good
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 4.5 V (Minimum VIN)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Operation at Light Loads
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4.1 External Power Sequencing

The TPS65262 has dedicated enable pin for each converter. The converter enable pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the converter with an active pull-down transistor on the ENx pin allows for a predictable power-down timing operation. Figure 7-3 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx pin.

A typical 1.4-µA current is charging ENx pin from input supply. When ENx pin voltage rise to typical 0.4 V, the internal V7V LDO turns on. A 3.6-µA pullup current is sourcing ENx. After ENx pin voltage reaches to 1.2 V typical, 3-µA hysteresis current sources to the pin to improve noise sensitivity. If all output voltages are in the regulation, PGOOD is asserted after PGOOD deglitch time.

GUID-7884145A-F889-445B-A17A-6B0F62BD5314-low.svgFigure 7-3 Startup Power Sequence