JAJSNJ1H データシート

JAJSNJ1H May 2013 – December 2021 TPS65310A-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RVJ|56
- MPQF275C

サーマルパッド・メカニカル・データ

発注情報

7.5 Electrical Characteristics

VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, T_J = –40°C to +150°C, unless otherwise noted

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
INPUT VOLTAGE-CURRENT CONSUMPTION
V_IN	Device operating range	Buck regulator operating range, Voltage on VIN and VINPROT pins		4		50	V
V_POR	Power-on reset threshold	Falling VIN		3.5	3.6	3.8	V
V_POR	Power-on reset threshold	Rising VIN		3.9	4.2	4.3	V
V_{POR_hyst}	Power-on reset hysteresis on VIN			0.47	0.6	0.73	V
I_LPM0	LPM0 current consumption⁽¹⁾	T_A = 25°C, All off, wake active, V_IN = 13 V, Total current into VSSENSE, VIN and VINPROT				44	μA
I_LPM0	LPM0 current (commercial vehicle application) consumption⁽¹⁾	T_A = 130°C, All off, wake active, V_IN = 24.5 V, Total current into VSSENSE, VIN and VINPROT				60	μA
I_ACTIVE1	ACTIVE total current consumption⁽²⁾	BUCK1 = on, V_IN= 13 V, EXTSUP = 0 V, Q_g of BUCK1 FETs = 15 nC, T_A = 25°C, Total current into VSSENSE, VIN and VINPROT			32		mA
I_ACTIVE123		BUCK1/2/3 = on, V_IN = 13 V, Q_g of BUCK1 FETs = 15 nC, T_A = 25°C, Total current into VSSENSE, VIN and VINPROT			40		mA
I_ACTIVE1235		BUCK1/2/3, LDO, BOOST, high-side switch = on, V_IN = 13 V, Q_g of BUCK1 FETs = 15 nC, T_A = 25°C, EXTSUP = 5 V from BOOST, Total current into VSSENSE, VIN and VINPROT			31		mA
I_{ACTIVE1235_noEXT}		BUCK1/2/3, LDO, BOOST, high-side switch = on, V_IN = 13 V, Q_g of BUCK1 FETs = 15 nC, T_A = 25°C, EXTSUP = open, Total current into VSENSE, VIN and VINPROT			53		mA
BUCK CONTROLLER (BUCK1)
V_BUCK1	Adjustable output voltage range			3		11	V
V_{Sense1_NRM}	Internal reference voltage in operating mode	VSENSE1 pin, load = 0 mA, Internal REF = 0.8 V		–1%		1%
V_S1-2	VS1-2 for forward OC in CCM	Maximum sense voltage VSENSE1 = 0.75 V (low duty cycle)		60	75	90	mV
V_S1-2	VS1-2 for forward OC in CCM	Minimum sense voltage VSENSE 1 = 1 V (negative current limit)		–65	–37.5	–23	mV
A_CS	Current-sense voltage gain	∆VCOMP1 / ∆ (VS1 - VS2)		4	8	12
t_{OCBUCK1_BLK}	RSTN and ERROR mode transition, when overcurrent is detected for > t_{OCBUCK1_BLK}				1		ms
t_{DEAD_BUCK1}	Shoot-through delay, blanking time				25		ns
ƒ_SWBUCK1	Switching frequency				f_OSC / 10		MHz
DC	Duty cycle	High-side minimum on time			100		ns
DC	Duty cycle	Maximum duty cycle			98.75%
EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER
I_Gpeak	Gate driver peak current	VREG = 5.8 V			0.6		A
R_{DSON_DRIVER}	Source and sink driver	I_G current for external MOSFET = 200 mA, VREG = 5.8 V, V_BOOT1-PH1 = 5.8 V			5	10	Ω
V_DIO1	Bootstrap diode forward voltage	I_BOOT1 = –200 mA, VREG-BOOT1		0.8		1.1	V
ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BOOST CONVERTER
gm_EA	Forward transconductance	COMP1/2/3/5 = 0.8 V; source and sink = 5 µA, test in feedback loop			0.9		m℧
A_EA	Error amplifier DC gain			60			dB
SYNCHRONOUS BUCK CONVERTER BUCK2/3
VSUP2/3	Supply voltage			3		11	V
V_BUCK2/3	Regulated output voltage range	I_load = 0 to 2 A, VSUPx = V_BUCK2/3 + I_load × 0.2 Ω		0.8		5.5	V
R_DSON-HS	R_DSON high-side switch	V_{BOOTx –PHx} = 5.8 V				0.20	Ω
R_DSON-LS	R_DSON low-side switch	VREG = 5.8 V				0.20	Ω
I_HS-Limit	High-side switch current limit	Static current limit test. In application L > 1 µH at I_HS-Limit and I_LS-Limit to limit dI / dt		2.4	2.9	3.5	A
I_LS-Limit	Low-side switch current limit	Static current limit test. In application L > 1 µH at I_HS-Limit and I_LS-Limit to limit dI / dt		2	2.5	3	A
VSUP_Lkg	VSUP leakage current	VSUP = 10 V for high side, controller disabled, T_J = 100°C			1	2	µA
ƒ_SWLBuck2/3	Buck switching frequency				f_OSC/5
V_Sense2/3	Feedback voltage	With respect to 800-mV internal reference		–1%		1%
DC_BUCK2/3	Duty cycle	High-side minimum on time			50		ns
DC_BUCK2/3	Duty cycle	Maximum duty cycle			99.8%
t_{DEAD_BUCK2/3}	Shoot-through delay				20		ns
COMP2/3_HTH	COMP2/3 input threshold low			0.9		1.5	V
COMP2/3_LTH	COMP2/3 input threshold high			VREG – 1.2		VREG – 0.3	V
R_{TIEOFF COMP23}	COMP2/3 internal tie-off	BUCK2/3 enabled. Resistor to VREG and GND, each		70	100	130	kΩ
V_{DIO2 3}	Bootstrap-diode forward voltage	I_BOOT1 = –200 mA, VREG-BOOT2, VREG-BOOT3			1.1	1.2	V
BOOST CONVERTER
V_Boost	Boost adjustable-output voltage range	Using 3.3-V input voltage, Ieak_switch ≤ 1 A		4.5		15	V
V_Boost	Boost adjustable-output voltage range	Using 3.3-V input voltage I_loadmax = 20 mA, I_{peak_switch} = 0.3 A		15		18.5	V
R_{DS-ON_BOOST}	Internal switch on-resistance	VREG = 5.8 V			0.3	0.5	Ω
V_Sense5	Feedback voltage	With respect to 800-mV internal reference		–1%		1%
f_SWLBOOST	Boost switching frequency				f_OSC / 5		MHz
DC_BOOST	Maximum internal-MOSFET duty cycle at f_SWLBOOST				90%
I_CLBOOST	Internal switch current limit			1		1.5	A
LINEAR REGULATOR LDO
VSUP4	Device operating range for LDO	Recommended operating range		3		7	V
V_LDO	Regulated output range	I_OUT = 1 mA to 350 mA		0.8		5.25	V
V_RefLDO	DC output voltage tolerance at VSENSE4	VSENSE4 = 0.8 V (regulated at internal reference), VSUP4 = 3 V to 7 V, I_OUT = 1 mA to 350 mA		–2%		2%
V_step1	Load step 1	VSENSE4 = 0.8 V (regulated at internal reference), I_OUT = 1 mA to 101 mA, C_LDO = 6 to 50 µF, t_rise = 1 µs		–2%		2%
V_Sense4	Feedback voltage	With respect to 800-mV internal reference		–1%		1%
V_Dropout	Dropout voltage	I_OUT = 350 mA, T_J = 25°C			127	143	mV
		I_OUT = 350 mA, T_J = 125°C			156	180
		I_OUT = 350 mA, T_J = 150°C			275	335
I_OUT	Output current	V_OUT in regulation		–350		–1	mA
I_LDO-CL	Output current limit	V_OUT = 0 V, VSUP4 = 3 V to 7 V		–1000		–400	mA
PSRR_LDO	Power-supply ripple rejection	V_ripple = 0.5 V_PP, I_OUT = 300 mA, C_LDO = 10 µF	Frequency = 100 Hz		60		dB
			Frequency = 4 kHz		50
			Frequency = 150 kHz		25
LDOns_10-100	Output noise 10 Hz – 100 Hz	10-µF output capacitance, V_LDO = 2.5 V				20	µV/√(Hz)
LDOns_100-1k	Output noise 100 Hz – 10 kHz	10-µF output capacitance, V_LDO = 2.5 V				6	µV/√(Hz)
C_LDO	Output capacitor	Ceramic capacitor with ESR range, C_{LDO_ESR} = 0 to 100 mΩ		6		50	µF
LED AND HIGH-SIDE SWITCH CONTROL
V_HSSENSE	Current-sense voltage	VINPROT – HSSENSE, high-side switch in current limit		370	400	430	mV
VCM_HSSENSE	Common-mode range for current sensing	See VINPROT		4		60	V
V_{HSOL_TH}	VINPROT – HSSENSE open load threshold	Ramping negative		5	20	35	mV
V_{HSOL_TH}	VINPROT – HSSENSE open load threshold	Ramping positive		26	38	50	mV
V_{HSOL_HY}	Open load hysteresis			10	18	28	mV
t_{HSOL_BLK}	Open-load blanking time			70	100	140	µs
V_{HS SC}	VINPROT – HSSENSE load short detection threshold	Ramping positive		88	92.5	96	% V_HSSENSE
V_{HS SC}	VINPROT – HSSENSE load short detection threshold	Ramping negative from load short condition		87	90	93	% V_HSSENSE
V_{HSSC_HY}	VINPROT – HSSENSE short circuit hysteresis			1			% V_HSSENSE
t_{HSS CL}	Net time in current-limit to disable driver			4	5	6	ms
t_{S HS}	Current-limit sampling interval				100		µs
VHSCTRL_OFF	Voltage at HSCTRL when OFF			VINPROT –0.5		VINPROT	V
V_GS	Clamp voltage between HSSENSE – HSCTRL			6.1	7.7	8.5	V
t_ON	Turn on time	Time from rising HSPWM until high-side switch in current limitation, ±5% settling				30	µs
t_ON	Turn on time	Time from rising HSPWM until high-side switch until voltage-clamp between HSSENSE – HSCTRL active (within V_GS limits)			30	60	µs
V_{OS_HS}	Overshoot during turnon	V_{OS_HS} = VINPROT - HSSENSE				400	mV
I_{CL_HSCTRL}	HSCTRL current limit			2	4.1	5	mA
R_{PU_HSCTRL}	Internal pullup resistors between VINPROT and HSCTRL			70	100	130	kΩ
R_{PU_HSCTRL-HSSENSE}	Internal pullup resistors between HSCTRL and HSSENSE			70	100	130	kΩ
V_{I_high}	High level input voltage	HSPWM, VIO = 3.3 V		2			V
V_{I_low}	Low level input voltage	HSPWM, VIO = 3.3 V				0.8	V
V_{I_hys}	Input voltage hysteresis	HSPWM, VIO = 3.3 V		150		500	mV
f_{HS_IN}	HSPWM input frequency	Design info, no device parameter		100		500	Hz
R_SENSE	External sense resistor	Design info, no device parameter		1.5		50	Ω
C_GS	External MOSFET gate source capacitance			100		2000	pF
C_GD	External MOSFET gate drain capacitance					500	pF
REFERENCE VOLTAGE
V_REF	Reference voltage				3.3		V
V_REF-tol	Reference voltage tolerance	I_VREF = 5 mA		–1%		1%
I_REFCL	Reference voltage current limit			10		25	mA
C_VREF	Capacitive load			0.6		5	µF
REFns_10-100	Output noise 10 Hz–100 Hz	2.2-µF output capacitance, I_VREF = 5 mA				20	µV/√(Hz)
REFns_100-1k	Output noise 100 Hz–10 kHz	2.2-µF output capacitance, I_VREF = 5 mA				6	µV/√(Hz)
V_{REF_OK}	Reference voltage OK threshold	Threshold, V_REF falling		2.91	3.07	3.12	V
V_{REF_OK}	Reference voltage OK threshold	Hysteresis		14	70	140	mV
T_{REF_OK}	Reference voltage OK deglitch time			10		20	µs
SHUTDOWN COMPARATOR (T_J = –55°C TO +150°C)
VT_REF	Shutdown comparator reference voltage	I_{VT_REF} = 20 µA. Measured as drop voltage with respect to VDVDD		1	17	500	mV
VT_REF	Shutdown comparator reference voltage	I_{VT_REF} = 600 µA. Measured as drop voltage with respect to VDVDD. No VT_REF short-circuit detection.		200	420	1100	mV
I_{VT_REFCL}	Shutdown comparator reference current limit	VT_REF = 0		0.6	1	1.4	mA
V_{VT_REF SH}	VT_REF short circuit detection	Threshold, VT_REF falling. Measured as drop voltage with respect to VDVDD		0.9	1.2	1.8	V
V_{VT_REF SH}	VT_REF short circuit detection	Hysteresis			130		mV
VT_TH-H	Input voltage threshold on VT, rising edge triggers shutdown	This feature is specified by design to work down to –55°C.		0.48	0.50	0.52	VT_REF
VT_TH-L	Input voltage threshold on VT, falling voltage enables device operation	This feature is specified by design to work down to –55°C.		0.46	0.48	0.52	VT_REF
VT_TOL	Threshold variation	VT_TH-H – VT_REF / 2, VT_TH-L – VT_REF / 2		–20		20	mV
I_{VT_leak}	Leakage current	T_J = –20°C to +150°C		–400		–50	nA
I_{VT_leak}	Leakage current	T_J = –55°C to –20°C		–200		–50	nA
VT_REF_OV	VT_REF overvoltage threshold	Threshold, VT_REF rising. Measured as drop voltage with respect to VDVDD		0.42	0.9	1.2	V
VT_REF_OV	VT_REF overvoltage threshold	Hysteresis			100		mV
T_{VT_REF_FLT}	VT_REF fault deglitch time	Overvoltage or short condition on VT_REF		10		20	µs
WAKE INPUT
V_{WAKE_ON}	Voltage threshold to enable device	WAKE pin is a level sensitive input		3.3		3.7	V
t_WAKE	Min. pulse width at WAKE to enable device	V_WAKE = 4 V to suppress short spikes at WAKE pin		10		20	µs
VBAT UNDERVOLTAGE WARNING
V_{SSENSETH_L}	VSSENSE falling-threshold low	SPI selectable, default after reset		4.3		4.7	V
V_{SSENSETH_H}	VSSENSE falling-threshold high	SPI selectable		6.2		6.8	V
V_SSENSE-HY	VSSENSE hysteresis				0.2		V
t_{VSSENSE_BLK}	Blanking time	V_VSENSE < V_{SSENSETH_xx} → IRQ asserted		10		35	µs
I_VSLEAK	Leakage current at VSSENSE	LPM0 mode, VSSENSE 55 V				1	µA
I_VSLEAK60		LPM0 mode, VSSENSE 60 V				100	µA
I_VSLEAK80		LPM0 mode, VSSENSE 80 V		5		25	mA
R_VSSENSE	Internal resistance from VSSENSE to GND	VSSENSE = 14 V, disabled in LPM0 mode		0.7	1	1.3	MΩ
VIN OVERVOLTAGE PROTECTION
V_{OVTH_H}	VIN overvoltage-shutdown threshold 1 (rising edge)	Selectable with SPI		50		60	V
V_{OVTH_L}	VIN overvoltage-shutdown threshold 2 (rising edge)	Selectable with SPI, default after reset		36		38	V
V_OVHY	VIN overvoltage hysteresis	Threshold 1		0.2	1.7	3	V
V_OVHY	VIN overvoltage hysteresis	Threshold 2; default after reset		1.5	2	2.5	V
t_{OFF BLK-H}	Overvoltage delay time	VIN > V_{OVTH_H} → GPFET off			1		µs
t_{OFF BLK-L}	Overvoltage blanking time	VIN > V_{OVTH_L} → GPFET off		10		20	µs
WINDOW WATCHDOG
t_timeout	Timeout	TESTSTART, TESTSTOP, VTCHECK , and RAMP mode: Begins after entering each mode. ACTIVE mode: WD timeout begins with rising edge of RESN		230	300	370	ms
t_WD	Watchdog window time	Spread spectrum disabled		18	20	22	ms
t_WD	Watchdog window time	Spread spectrum enable		19.8	22	24.2	ms
t_{WD_FAIL}	Closed window time				t_WD / 4
t_{WD_BLK}	WD filter time					0.5	µs
V_{I_high}	High level input voltage	WD, VIO = 3.3 V		2			V
V_{I_low}	Low level input voltage	WD, VIO = 3.3 V				0.8	V
V_{I_hys}	Input voltage hysteresis	WD, VIO = 3.3 V		150		500	mV
RESET AND IRQ BLOCK
t_RESNHOLD	RESN hold time			1.8	2	2.2	ms
V_RESL	Low level output voltage at RESN, PRESN and IRQ	VIN ≥ 3 V, IxRESN = 2.5 mA		0		0.4	V
V_RESL	Low level output voltage at RESN and PRESN	VIN = 0 V, VIO = 1.2 V, IxRESN = 1 mA		0		0.4	V
I_RESLeak	Leakage current at RESN, PRESN and IRQ	V_test = 5.5 V				1	µA
N_RES	Number of consecutive reset events for transfer to LPM0				7
t_IRQHOLD	IRQ hold time	After V_VSENSE < V_SSENSETH for t_{VSSENSE_BLK}		10		20	µs
t_{DR IRQ PRESN}	Rising edge delay of IRQ to rising edge of PRESN				2		µs
t_{DF RESN_PRESN}	Falling edge delay of RESN to PRESN / IRQ				2		µs
EXTERNAL PROTECTION
VCLAMP	Gate to source clamp voltage	VIN – GPFET, 100 µA		14		20	V
IGPFET	Gate turn on current	VIN = 14 V, GPFET = 2 V		15		25	µA
RDSONGFET	Gate driver strength	VIN = 14 V, turn off				25	Ω
THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION
T_SDTH	Thermal shutdown	Junction temperature		160	175		°C
T_SDHY	Hysteresis				20		°C
t_SD-BLK	Blanking time before thermal shutdown			10		20	µs
T_OTTH	Overtemperature flag	Overtemperature flag is implemented as local temp sensors and expected to trigger before the thermal shutdown		150	165		°C
T_OTHY	Hysteresis				20		°C
t_{OT_BLK}	Blanking time before thermal over temperature			10		20	µs
VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER
V_{MONTH_L}	Voltage monitor reference, falling edge	REF = 0.8 V		90	92	94	%
V_{MONTH_H}	Voltage monitor reference, rising edge	REF = 0.8 V		106	108	110	%
V_{MON_HY}	Voltage monitor hysteresis				2		%
V_{VIOMON_TH}	Undervoltage monitoring at VIO – falling edge			3		3.13	V
V_{VIOMON_HY}	UV_VIO hysteresis				0.05		V
t_{VMON_BLK}	Blanking time between UV or OV condition to RESN low	UV/OV = BUCK1/2/3 UV = VIO		10		20	µs
t_{VMONTHL_BLK}	Blanking time between undervoltage condition to ERROR mode transition or corresponding SPI bit	BUCK1/2/3 → ERROR mode LDO or BOOST → SPI bit set or turn off			1		ms
t_{VMONTHL_BLK1}	Blanking time between undervoltage condition to ERROR mode transition	VIO only		10		20	µs
t_{VMONTHH_BLK1}	Blanking time between overvoltage condition to ERROR mode transition	BUCK1/2/3 → ERROR mode VIO has no OV protection		10		20	µs
t_{VMONTHH_BLK2}	Blanking time LDO and BOOST overvoltage condition to corresponding SPI bit or ERROR mode	LDO or BOOST (ACTIVE mode) → SPI bit set or turn off LDO (VTCHECK or RAMP mode) → ERROR mode		20		40	µs
GND LOSS
V_GLTH-low	GND loss threshold low	GND to PGNDx		–0.31	–0.25	–0.19	V
V_GLTH-high	GND loss threshold high	GND to PGNDx		0.19	0.25	0.31	V
t_GL-BLK	Blanking time between GND loss condition and transition to ERROR state			5		20	µs
POWER-UP SEQUENCING
t_START1	Soft start time of BOOST	From start until exceeding V_{MONTH_L} + V_{MON_HY} Level		0.7		2.7	ms
t_START2	Soft start time of BUCK1/2/3 and LDO	From start until exceeding V_{MONTH_L} + V_{MON_HY} Level		0.5		2	ms
t_START	Startup DVDD regulator	From start until exceeding V_{MONTH_L} + V_{MON_HY} Level				3	ms
t_SEQ2	Sequencing time from start of BUCK1 to BUCK2 and BOOST	Internal SSDONE_BUCK1 signal				3	ms
t_WAKE-RES	Startup time from entering TESTSTART to RESN high	GPFET = IRFR6215				14	ms
t_SEQ1	Sequencing time from start of BOOST to BUCK3	Internal SSDONE_BOOST signal		1		4	ms
INTERNAL VOLTAGE REGULATORS (T_J = –55°C to +150°C)
V_REG	Internal regulated supply	I_VREG = 0 mA to 50 mA, VINPROT = 6.3 V to 40 V and EXTSUP = 6.3 V to 12 V		5.5	5.8	6.1	V
V_EXTSUP-TH	Switch over voltage	I_VREG = 0 mA to 50 mA and EXTSUP ramping positive, ACTIVE mode		4.4	4.6	4.8	V
V_EXTSUP-HY	Switch over hysteresis			100	200	300	mV
V_REGDROP	Dropout voltage on VREG	I_VREG = 50 mA, EXTSUP = 5 V / VINPROT = 5 V and EXTSUP = 0 V / VINPROT = 4 V				200	mV
I_{REG_CL}	Current limit on VREG	EXTSUP = 0 V, VREG = 0 V		–250		–50	mA
I_{REG_EXTSUP_CL}	Current limit on VREG	EXTSUP ≥ 4.8 V, VREG = 0 V		–250		–50	mA
C_VREG	Capacitive load			1.2	2.2	3.3	µF
V_REG-OK	VREG undervoltage threshold	VREG rising		3.8	4	4.2	V
V_REG-OK	VREG undervoltage threshold	Hysteresis		350	420	490	mV
VDVDD	Internal regulated low voltage supply			3.15	3.3	3.45	V
VDVDD UV	DVDD undervoltage threshold	DVDD falling		2.1			V
VDVDD OV	DVDD overvoltage threshold	DVDD rising				3.8	V
t_{DVDD OV}	Blanking time from DVDD overvoltage condition to shutdown mode transition			10		20	µs
GLOBAL PARAMETERS
R_PU	Internal pullup resistor at CSN pin			70	100	130	kΩ
R_PD	Internal pulldown resistor at pins: HSPWM , SDI, SCK, WD, S2⁽³⁾			70	100	130	kΩ
R_PD-WAKE	Internal pulldown resistor at WAKE pin			140	200	260	kΩ
I_LKG	Input pullup current at the VSENSE1–5 and VMON1–3 pins	V_TEST = 0.8 V		–200	–100	–50	nA
f_OSC	Internal oscillator used for buck or boost switching frequency			4.6	4.9	5.2	MHz
f_spread	Spread-spectrum frequency range			0.8 × f_OSC		f_OSC	MHz
SPI
V_{I_high}	High-level input voltage	CSN, SCK, SDI; VIO = 3.3 V		2			V
V_{I_low}	Low-level input voltage	CSN, SCK, SDI; VIO = 3.3 V				0.8	V
V_{I_hys}	Input voltage hysteresis	CSN, SCK, SDI; VIO = 3.3 V		150		500	mV
V_{O_high}	SDO-output high voltage	VIO = 3.3 V I_SDO = 1 mA		3			V
V_{O_low}	SDO-output low voltage	VIO = 3.3 V I_SDO = 1 mA				0.2	V
CSDO	SDO capacitance					50	pF

(1) The quiescent current specification does not include the current flow through the external feedback resistor divider. Quiescent current is non-switching current, measured with no load on the output with VBAT = 13 V.

(2) Total current consumption measured on the EVM includes switching losses.

(3) RAMP and ACTIVE only.