8.1.1 Input, Output, and Bias Capacitor Requirements

The TPS742 family does not require any output capacitor for stability. If an output capacitor is needed, the device is designed to be stable for all available types and values of output capacitance. The device is also stable with multiple capacitors in parallel, which can be of any type or value.

The capacitance required on the IN and BIAS pins is strongly dependent on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for V_IN and V_BIAS is 1μF. If V_IN and V_BIAS are connected to the same supply, the recommended minimum capacitor for V_BIAS is 4.7 μF. Use good quality, low ESR capacitors on the input; ceramic X5R and X7R capacitors are preferred. Place these capacitors as close to the pins as possible for optimum performance.

8.1.2 Transient Response

The TPS742 family of devices were designed to have transient response within 5% for most applications without any output capacitor. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300 mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance would do. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient at the expense of a slightly longer V_OUT recovery time. See Figure 20 in the Typical Characteristics section. Because the TPS742 devices are stable without an output capacitor, many applications may allow for little or no capacitance at the LDO output. For these applications, local bypass capacitance for the device under power may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive high-value capacitors at the LDO output.

8.1.3 Dropout Voltage

The TPS742 family of devices offers industry-leading dropout performance, making this family well-suited for high-current low V_IN/low V_OUT applications. The extremely low dropout of the TPS742 allows the device to be used in place of a DC-DC converter and still achieve good efficiency. This efficiency allows the user to rethink the power architecture for their applications to achieve the smallest, simplest, and lowest cost solution.

There are two different specifications for dropout voltage with the TPS742 devices. The first specification (illustrated in Figure 24) is referred to as V_IN Dropout, and is for users who wish to apply an external bias voltage to achieve low dropout. This specification assumes that V_BIAS is at least 1.62 V above V_OUT, which is the case for V_BIAS when powered by a 3.3-V rail with 5% tolerance and with V_OUT = 1.5 V. If V_BIAS is higher than 3.3 V × 0.95 or V_OUT is less than 1.5 V, V_IN dropout is less than specified.

Figure 24. Typical Application of the TPS742 Using an Auxiliary Bias Rail

The second specification (shown in Figure 25) is referred to as V_BIAS Dropout, and is for users who wish to tie IN and BIAS together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because V_BIAS provides the gate drive to the pass FET and therefore must be 1.4 V above V_OUT. Because of this usage, IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of the IC package.

Figure 25. Typical Application of the TPS742 Without an Auxiliary Bias

8.1.4 Output Noise

The TPS742 devices provide low-output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001-μF soft-start capacitor, the output noise is reduced by half and is typically 30 μV_RMS for a 1.2-V output (10 Hz to 100 kHz). Because most of the output noise is generated by the internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001-μF soft-start capacitor is given in Equation 1.

Equation 1.

The low-output noise of the TPS742 makes the device a good choice for powering transceivers, PLLs, or other noise-sensitive circuitry.

8.1.5 Programmable Soft-Start

The TPS742 devices feature a programmable, monotonic, voltage-controlled soft start that is set with an external capacitor (C_SS). This feature is important for many applications, because power-up initialization problems are eliminated when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, minimizing start-up transients to the input power bus.

To achieve a linear and monotonic soft-start, the TPS742 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-start charging current (I_SS), soft-start capacitance (C_SS), and the internal reference voltage (V_REF), and can be calculated using Equation 2:

Equation 2.

If large output capacitors are used, the device current limit (I_CL) and the output capacitor may set the start-up time. In this case, the start-up time is given by Equation 3:

Equation 3.

V_OUT(NOM) is the nominal set output voltage as set by the user, C_OUT is the output capacitance, and I_CL(MIN) is the minimum current limit for the device. In applications where monotonic start-up is required, the soft-start time given by Equation 2 must be set to be greater than Equation 3.

The maximum recommended soft-start capacitor is 0.015 μF. Larger soft-start capacitors can be used and do not damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft-start capacitor when enabled. Soft-start capacitors larger than 0.015 μF could be a problem in applications where the user must rapidly pulse the enable pin and still requires the device to soft-start from ground. C_SS must be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. See Table 2 for suggested soft-start capacitor values.

Equation 4.

where

• t_SS(s) = soft-start time in seconds

8.1.6 Sequencing Requirements

The device can have V_IN, V_BIAS, and V_EN sequenced in any order without causing damage to the device. However, for the soft-start function to work as intended, certain sequencing rules must be applied. Enabling the device after V_IN and V_BIAS are present is preferred, and can be accomplished using a digital output from a processor or supply supervisor. An analog signal from an external RC circuit, as shown in Figure 26, can also be used as long as the delay time is long enough for V_IN and V_BIAS to be present.

Figure 26. Soft-Start Delay Using an RC Circuit on Enable

If a signal is not available to enable the device after IN and BIAS, simply connecting EN to IN is acceptable for most applications as long as V_IN is greater than 1.1 V and the ramp rate of V_IN and V_BIAS is faster the set soft-start ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply minus the dropout voltage until the set output voltage is reached. If EN is connected to BIAS, the device does soft-start as programmed provided that V_IN is present before V_BIAS. If V_BIAS and V_EN are present before V_IN is applied and the set soft-start time has expired then V_OUT tracks V_IN.

Table 3. Standard 1% Resistor Values for Programming the Output Voltage
(See Equation 5)

8.2.1 Design Requirements

The design goals are V_IN = 1.8 V, V_OUT = 1.5 V, and I_OUT = 1 A (maximum). The design optimizes transient response and meets a 1-ms start-up time with a start-up dominated by the soft-start feature. The input supply comes from a supply on the same circuit board. The available system rails for V_BIAS are 2.7 V, 3.3 V, and 5 V.

The design space consists of C_IN, C_OUT, C_BIAS, C_SS, V_BIAS, R₁, R₂, and R₃, and the circuit is from Figure 27.

This example uses a V_IN of 1.8 V, with a V_BIAS of 2.5 V.

8.2.2 Detailed Design Procedure

This is assuming the table for the standard capacitor values is put back in as Table 1.

Utilizing Table 3, we select R1 = 4.12 kΩ for V_OUT = 1.5 V. and R2 = 4.75 kΩ. Using Table 1, we select C_SS = 1000 pF for a 1-ms typical start-up time. For optimal performance, we use the 5-V rail for a Bias supply. An R3 of 100 kΩ is selected as the PG bus is used by other devices with additional 100-kΩ pullup resistors.

A C_IN of 10 µF is used for better transient performance on the input supply, a C_BIAS of 1 µF is used to ensure the Bias supply is solid, and a C_OUT of 1 µF is used to provide some local capacitance on the output.

8.2.3 Application Curves

Figure 28. V_IN Dropout Voltage vs
I_OUT and Temperature (T_J)

Figure 30. Output Load Transient Response

Figure 29. V_BIAS Line Transient (1.5 A)

Figure 31. Turnon Response