JAJSL23B January   2021  – January 2022 TPS785-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Foldback Current Limit
      2. 7.3.2 Output Enable
      3. 7.3.3 Active Discharge
      4. 7.3.4 Undervoltage Lockout (UVLO) Operation
      5. 7.3.5 Dropout Voltage
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Adjustable Device Feedback Resistors
      4. 8.1.4 Load Transient Response
      5. 8.1.5 Exiting Dropout
      6. 8.1.6 Dropout Voltage
      7. 8.1.7 Reverse Current
      8. 8.1.8 Feed-Forward Capacitor (CFF)
      9. 8.1.9 Power Dissipation (PD)
        1. 8.1.9.1 Estimating Junction Temperature
        2. 8.1.9.2 Recommended Area for Continuous Operation
        3. 8.1.9.3 Power Dissipation versus Ambient Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Additional Layout Considerations
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure 7-4 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:

  • Region A: The device does not start until the input reaches the UVLO rising threshold.
  • Region B: Normal operation, regulating device.
  • Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The output may fall out of regulation but the device remains enabled.
  • Region D: Normal operation, regulating device.
  • Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising threshold is reached by the input voltage and a normal start-up follows.
  • Region F: Normal operation followed by the input falling to the UVLO falling threshold.
  • Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The output falls because of the load and active discharge circuit.

GUID-49F20F4A-F2C2-44BE-B83F-77BEAB2529E1-low.gifFigure 7-4 Typical UVLO Operation