JAJSH81B April 2019 – February 2021 TPS929120-Q1
PRODUCTION DATA
The TPS929120-Q1 has a 8-bit register CALC_CONFCRC to store the calculated CRC result for all registers listed in Table 7-12. The master controller can read back the data in CALC_CONFCRC to quickly check any untended change of registers without reading back all configuration registers. The CRC algorithm is same to the EEPROM CRC diagnostics as described in EEPROM CRC Error in Normal State. The initial code for CRC is FFh as well.