JAJSOC4A november   2022  – april 2023 TPSF12C1-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active EMI Filtering
        1. 8.3.1.1 Schematics
      2. 8.3.2 Capacitive Amplification
      3. 8.3.3 Integrated Line Rejection Filter
      4. 8.3.4 Compensation
      5. 8.3.5 Remote Enable
      6. 8.3.6 Supply Voltage UVLO Protection
      7. 8.3.7 Thermal Shutdown Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
  10. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – AEF Circuit for High-Density On-Board Charger (OBC) in Electric Vehicles (EVs)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sense Capacitors
          2. 9.2.1.2.2 Inject Capacitor
          3. 9.2.1.2.3 Compensation Network
          4. 9.2.1.2.4 Injection Network
          5. 9.2.1.2.5 Surge Protection
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DYY|14
サーマルパッド・メカニカル・データ
発注情報

Schematics

Figure 9-2 shows a schematic of a conventional two-stage passive EMI filter in kilowatt-scale, grid-connected applications. L, N and PE refer to the respective live, neutral and protective earth connections. Multistage filters as shown provide high roll-off and are widely used in high-power AC line applications where CM noise is often more challenging to mitigate than DM noise. The low-order switching harmonics usually dictate the size of the reactive filter components based on the required corner frequency (or multiple corner frequencies in multistage designs).

GUID-20230411-SS0I-MLGQ-LRB2-Q7VJWGFQ1XQ9-low.svg Figure 8-1 Circuit Schematic of a Single-Phase Passive Filter and Corresponding Active Filter Solution for CM Attenuation

Also included in Figure 9-2 is the corresponding active filter design. The active circuit replaces the two Y-capacitors positioned between the CM chokes with a single-phase AEF circuit using the TPSF12C1-Q1 to provide a lower impedance shunt path for CM currents. The sense pins of the TPSF12C1-Q1 interface with the power lines using a set of Y-rated sense capacitors, typically 680 pF, and feed into an internal high-pass filter and signal combiner. The IC rejects both line-frequency (50-Hz or 60-Hz) AC voltage as well as DM disturbances, while amplifying high-frequency CM disturbances and maintaining closed-loop stability using an external tunable damping circuit.

The X-capacitor placed between the two CM chokes in Figure 9-2 effectively provide a low-impedance path between the power lines from a CM standpoint, typically up to low-MHz frequencies. This allows current injection onto one power line (usually neutral or the power line routed closest to the IC) using only one inject capacitor.