JAJSOC4A november   2022  – april 2023 TPSF12C1-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active EMI Filtering
        1. 8.3.1.1 Schematics
      2. 8.3.2 Capacitive Amplification
      3. 8.3.3 Integrated Line Rejection Filter
      4. 8.3.4 Compensation
      5. 8.3.5 Remote Enable
      6. 8.3.6 Supply Voltage UVLO Protection
      7. 8.3.7 Thermal Shutdown Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – AEF Circuit for High-Density On-Board Charger (OBC) in Electric Vehicles (EVs)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sense Capacitors
          2. 9.2.1.2.2 Inject Capacitor
          3. 9.2.1.2.3 Compensation Network
          4. 9.2.1.2.4 Injection Network
          5. 9.2.1.2.5 Surge Protection
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DYY|14
サーマルパッド・メカニカル・データ
発注情報

9.4.1 Layout Guidelines

The following list summarizes the essential guidelines for PCB layout and component placement to optimze AEF performance. Figure 9-9 and Figure 9-10 show a recommended layout for the TPSF12C1-Q1 circuit specifically with optimized placement and routing of the IC and small-signal components. Figure 9-11 shows an example of a single-phase filter board design with with CM chokes, X-capacitors, Y-capacitors, protection components (such as varistors and X-capacitor discharge resistors), and AEF circuit. The filter board includes a receptacle for easy connection of a single-phase AEF daughtercard EVM (instead of using the AEF components on the PCB).

  • Position the sense and inject capacitors between the CM chokes near the X-capacitor that couples the injected signal to the other power line. Avoid placement close to the CM choke windings that may result in parasitic coupling to the sense and inject capacitors.
  • Maintain adequate clearance spacing between high-voltage and low-voltage traces. As an example, Figure 9-11 has 150 mils (3.8 mm) copper-to-copper spacing from power lines (live and neutral) to chassis ground.
  • Route the sense lines S1 and S2 away from the INJ line. Avoid coupling between the sense and inject traces.
  • Use a solid ground connection between the TPSF12C1-Q1 and the filter board. Minimize parasitic inductance from the AEF circuit return to the chassis ground connections on the board.
  • Place a ceramic capacitor close to VDD and IGND. Minimize the loop area to the VDD and IGND pins.
  • Place the compensation network copnponents close to the COMP1 and COMP2 pins. Reduce noise sensitivity of the feedback compensation network path by placing components RG, CG1 and CG2 close to the COMP pins. COMP2 is the inverting input to the AEF anplifier and represents a high-impedance node sensitive to noise.
  • Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal impedance. Provide adequate heatsinking for the TPSF12C1-Q1 to keep the junction temperature below 150°C. A top-side ground plane is an important heat-dissipating area. Use several heat-sinking vias to connect REFGND (pin 9) and IGND (pin 14) to ground copper on other layers.