8.6.1.3 DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
DP01EQ_SEL is shown in Table 15.
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This register controls the receiver equalization setting for the DisplayPort receivers 0 and 1.
Table 15. DP01EQ_SEL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-4 |
DP1EQ_SEL |
RH/W |
0x0 |
Field selects EQ for DP lane 1 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 1 based on value written to this field.
|
3-0 |
DP0EQ_SEL |
RH/W |
0x0 |
Field selects EQ for DP lane 0 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 0 based on value written to this field.
|