JAJSCK9B september   2016  – december 2021 UCC21521

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programmable Dead Time
    5. 7.5 Powerup UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21521
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Gate to Source Resistor Selection
        5. 9.2.2.5 Estimate Gate Driver Power Loss
        6. 9.2.2.6 Estimating Junction Temperature
        7. 9.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.7.1 Selecting a VCCI Capacitor
          2. 9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.7.3 Select a VDDB Capacitor
        8. 9.2.2.8 Dead Time Setting Guidelines
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC21521 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output low, regardless of the status of the input pins (INA and INB).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 8-1). In this condition, the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically less than 1.5 V, when no bias power is available.

GUID-0F176833-009C-4BA2-9E90-75BA88FD09B6-low.gifFigure 8-1 Simplified Representation of Active Pulldown Feature

The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC21521 also has an internal under voltage lock out (UVLO) protection feature. The device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And a signal will cease to be delivered when that pin receives a voltage less than VVCCI_OFF. Also, like the UVLO for VDD, there is hysteresis (VVCCI_HYS) to ensure stable operation.

All versions of the UCC21521 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

Table 8-1 UCC21521 VCCI UVLO Feature Logic
CONDITION INPUTS OUTPUTS
INA INB OUTA OUTB
VCCI-GND < VVCCI_ON during device start up H L L L
VCCI-GND < VVCCI_ON during device start up L H L L
VCCI-GND < VVCCI_ON during device start up H H L L
VCCI-GND < VVCCI_ON during device start up L L L L
VCCI-GND < VVCCI_OFF after device start up H L L L
VCCI-GND < VVCCI_OFF after device start up L H L L
VCCI-GND < VVCCI_OFF after device start up H H L L
VCCI-GND < VVCCI_OFF after device start up L L L L
Table 8-2 UCC21521 VDD UVLO Feature Logic
CONDITION INPUTS OUTPUTS
INA INB OUTA OUTB
VDD-VSS < VVDD_ON during device start up H L L L
VDD-VSS < VVDD_ON during device start up L H L L
VDD-VSS < VVDD_ON during device start up H H L L
VDD-VSS < VVDD_ON during device start up L L L L
VDD-VSS < VVDD_OFF after device start up H L L L
VDD-VSS < VVDD_OFF after device start up L H L L
VDD-VSS < VVDD_OFF after device start up H H L L
VDD-VSS < VVDD_OFF after device start up L L L L