JAJSR77 September   2023 UCC21738-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Propagation Delay
      1. 7.1.1 Regular Turn-OFF
    2. 7.2 Input Deglitch Filter
    3. 7.3 Active Miller Clamp
      1. 7.3.1 External Active Miller Clamp
    4. 7.4 Undervoltage Lockout (UVLO)
      1. 7.4.1 VCC UVLO
      2. 7.4.2 VDD UVLO
    5. 7.5 Overcurrent (OC) Protection
      1. 7.5.1 OC Protection with Soft Turn-OFF
    6. 7.6 ASC Support
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
      2. 8.3.2  Driver Stage
      3. 8.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 8.3.4  Active Pulldown
      5. 8.3.5  Short Circuit Clamping
      6. 8.3.6  External Active Miller Clamp
      7. 8.3.7  Overcurrent and Short Circuit Protection
      8. 8.3.8  Soft Turn-off
      9. 8.3.9  Fault (FLT), Reset, and Enable (RST/EN)
      10. 8.3.10 ASC Support and APWM Monitor
    4. 8.4 Device Functional Modes
  10. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Filters for IN+, IN-, and RST/EN
        2. 9.2.2.2 PWM Interlock of IN+ and IN-
        3. 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 9.2.2.4 RST/EN Pin Control
        5. 9.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 9.2.2.6 External Active Miller Clamp
        7. 9.2.2.7 Overcurrent and Short Circuit Protection
          1. 9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
          2. 9.2.2.7.2 Protection Based on Desaturation Circuit
          3. 9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
        8. 9.2.2.8 Higher Output Current Using an External Current Buffer
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Application Information

The device is very versatile because of the strong drive strength, wide range of the output power supply, high isolation ratings, high CMTI, and superior protection and sensing features. The 1.5-kVRMS working voltage and 12.8-kVPK surge immunity can support both SiC MOSFET and IGBT modules with DC bus voltage up to 2121 V. The device can be used in both low power and high power applications such as traction inverter in HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies, and so forth. The device can drive the high power SiC MOSFET module, IGBT module, or paralleled discrete device directly without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows the driver to have more control to the power semiconductor and saves cost and space of the board design. The UCC21738-Q1 can also be used to drive very high power modules or paralleled modules with external buffer stage. The input side can support power supply and microcontroller signals from 3.3 V to 5 V, and the device level shifts the signal to the output side through the reinforced isolation barrier. The device has a wide output power supply range from 13 V to 33 V and supports a wide range of negative power supply. This allows the driver to be used in SiC MOSFET applications, IGBT applications, and many others. The 12-V UVLO benefits the power semiconductor with lower conduction loss and improves system efficiency. As a reinforced isolated single channel driver, the device can be used to drive either a low-side or high-side driver.

The device features extensive protection and monitoring features, which can monitor, report, and protect the system from various fault conditions.

  • Fast detection and protection for an overcurrent and short circuit fault. The feature is preferable in a split source SiC MOSFET module or a split emitter IGBT module. For modules with no integrated current mirror or paralleled discrete semiconductors, the traditional desaturation circuit can be modified to implement short circuit protection. The semiconductor is shut down when a fault is detected and the FLT pin is pulled down to indicate the fault detection. The device is latched unless a reset signal is received from the RST/EN pin.
  • Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during an overcurrent and short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is limited.
  • UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to be in UVLO mode, the output is pulled down and the RDY pin indicates the power supply is lost. The device is back to normal operation mode once the power supply is out of the UVLO status. The power-good status can be monitored from the RDY pin.
  • Active short circuit feature creates phase-to-phase short circuit in the three-phase inverter to protect the battery from overvoltage breakdown.
  • Active Miller clamp feature protects the power semiconductor from false turn on by driving an external MOSFET. This feature allows flexibility of board layout design and the pulldown strength of the Miller clamp FET.
  • Enable and disable function through the RST/EN pin.
  • Short circuit clamping
  • Active pulldown