JAJSDB5 June   2017 UCC28730-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 HV (High Voltage Startup)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CBC (Cable Compensation)
        6. 7.3.1.6 VS (Voltage Sense)
        7. 7.3.1.7 CS (Current Sense)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage Regulation
      4. 7.3.4 Primary-Side Constant Current Regulation
      5. 7.3.5 Wake-Up Detection and Function
      6. 7.3.6 Valley-Switching and Valley-Skipping
      7. 7.3.7 Startup Operation
      8. 7.3.8 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-By Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CVDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
        8. 8.2.2.8 VS Wake-Up Detection
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの項目表記
        1. 11.1.1.1  容量項(ファラッド単位)
        2. 11.1.1.2  デューティ・サイクル項
        3. 11.1.1.3  周波数項(ヘルツ単位)
        4. 11.1.1.4  電流項(アンペア単位)
        5. 11.1.1.5  電流および電圧のスケーリング項
        6. 11.1.1.6  トランスの項
        7. 11.1.1.7  電力項(ワット単位)
        8. 11.1.1.8  抵抗項(オーム単位)
        9. 11.1.1.9  タイミング項(秒単位)
        10. 11.1.1.10 DC電圧項(ボルト単位)
        11. 11.1.1.11 AC電圧項(ボルト単位)
        12. 11.1.1.12 効率項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

D Package
7-Pin SOIC
Top View
UCC28730-Q1 pin_lusbl5.gif

Pin Functions(1)

PIN I/O DESCRIPTION
NAME NO.
VDD 1 P VDD is the bias supply input pin to the controller. A carefully-placed by-pass capacitor to GND is required on this pin.
VS 2 I Voltage Sense is an input used to provide voltage feed-back and demagnetization timing to the controller for output voltage regulation, frequency limiting, constant-current control, line voltage detection, and output over-voltage detection. This pin is connected to a voltage divider between an auxiliary winding and GND. The value of the upper resistor of this divider is used to program the AC-mains run and stop thresholds and line compensation at the CS pin. This input also detects a qualified wake-up signal when operating in the Wait state.
CBC 3 I CaBle Compensation is a programming pin for compensation of cable voltage drop. Cable compensation is programmed with a resistor to GND.
GND 4 G The GrouND pin is both the reference pin for the controller and the low-side return for the drive output. Special care should be taken to return all AC decoupling capacitors as close as possible to this pin and avoid any common trace length with power and signal return paths.
CS 5 I Current Sense input connects to a ground-referenced current-sense resistor in series with the power switch. The resulting voltage is used to monitor and control the peak primary current. A series resistor can be added to this pin to compensate the peak switch current levels as the rectified bulk voltage varies.
DRV 6 O DRiVe is an output used to drive the gate of an external high-voltage MOSFET switching transistor.
HV 7 I The High Voltage pin connects directly to the rectified bulk voltage and provides charge to the VDD capacitor for start-up of the power supply.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output