JAJSRJ4 October   2023 UCC44273

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 説明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Low Propagation Delays
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Threshold Type
        2. 8.2.2.2 VDD Bias Supply Voltage
        3. 8.2.2.3 Peak Source and Sink Currents
        4. 8.2.2.4 Propagation Delay
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
      4. 8.4.4 Power Dissipation
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 1.

Equation 1. GUID-03DB13C4-29D1-4A34-9012-33A645C859F2-low.gif

The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver. The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through and so on). The UCC44273 features very low quiescent currents (less than 1 mA, refer to Figure 6-4) and contains internal logic to eliminate any shoot-through in the output-driver stage. Thus the effect of the PDC on the total power dissipation within the gate driver can be safely assumed to be negligible.

The power dissipated in the gate-driver package during switching (PSW) depends on the following factors:

  • Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to input bias supply voltage VDD due to low VOH drop-out).
  • Switching frequency.
  • Use of external-gate resistors.

When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly easy. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 2.

Equation 2. GUID-1BBBDCBA-CEAF-420C-A717-688AA811925D-low.gif

Where

  • CLOAD is load capacitor
  • VDD is bias voltage feeding the driver

There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss given by Equation 3.

Equation 3. GUID-6C65D6F6-A7CC-4DC0-851F-C156E68A8E2A-low.gif

where

  • ƒSW is the switching frequency

The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when charging a capacitor. This is done by using the equation, QG = CLOAD x VDD, to provide the following equation for power:

Equation 4. GUID-9DB53671-47F6-4650-86AF-8EAE92817147-low.gif

This power PG is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or turned off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated in Equation 5.

Equation 5. GUID-CA451E8D-49FA-439A-B9F8-EF751BBC09C2-low.gif

where

  • ROFF = ROL
  • RON (effective resistance of pull-up structure) = 1.4 x ROL