SLUSDC1 September   2018 UCD90320U

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Application
  4. Revision History
  5. Description Continued
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Non-Volatile Memory Characteristics
    7. 7.7 I2C/PMBus Interface Timing Requirements
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TI Fusion Digital Power Designer software
      2. 8.3.2 PMBUS Interface
      3. 8.3.3 Rail Setup
    4. 8.4 Device Functional Modes
      1. 8.4.1  Rail Monitoring Configuration
      2. 8.4.2  GPI Configuration
      3. 8.4.3  Rail Sequence Configuration
      4. 8.4.4  Fault Responses Configuration
      5. 8.4.5  GPO Configuration
        1. 8.4.5.1 Command Controlled GPO
        2. 8.4.5.2 Logic GPO
      6. 8.4.6  Margining Configuration
      7. 8.4.7  Pin Selected Rail States Configuration
      8. 8.4.8  Watchdog Timer
      9. 8.4.9  System Reset Function
      10. 8.4.10 Cascading Multiple Devices
      11. 8.4.11 Rail Monitoring
      12. 8.4.12 Status Monitoring
      13. 8.4.13 Data and Error Logging to EEPROM Memory
      14. 8.4.14 Black Box First Fault Logging
      15. 8.4.15 PMBus Address Selection
      16. 8.4.16 ADC Reference
      17. 8.4.17 Device Reset
      18. 8.4.18 Brownout
      19. 8.4.19 Internal Fault Management
      20. 8.4.20 Single Event Upset
    5. 8.5 Device Configuration and Programming
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

System Reset Function

The system reset function can generate a programmable system reset signal through a GPIO pin. The system reset signal is de-asserted when the selected rail voltages reach their respective Power Good On thresholds and the selected GPIs are asserted, plus a programmable delay time. These are the available options for the system-reset delay times.

  • 0 ms
  • 1 ms
  • 2 ms
  • 4 ms
  • 8 ms
  • 16 ms
  • 32 ms
  • 64 ms
  • 128 ms
  • 256 ms
  • 512 ms
  • 1.02 s
  • 2.05 s
  • 4.10s
  • 8.19 s
  • 16.38 s
  • 32.8 s

The System Reset signal can be asserted immediately when any of the selected rail voltage falls below Power Good Off threshold, or any selected GPI is de-asserted. Alternatively, the System Reset signal can be configured as a pulse once Power Good On is achieved. An example in Figure 26 illustrates the difference of the two configurations. The pulse width can be configured between 0.001 s to 32.256 s. See the UCD90320U Sequencer and System Health Controller PMBus Command Reference for pulse width configuration details.

UCD90320U sys_reset_powergood_SLVSCW0.gifFigure 26. System Reset With and Without Pulse Setting (Active Low)

The System Reset signal can also integrate watchdog timer. An example is shown in Figure 27. In Figure 27, the first delay on System Reset is for the initial reset release that would enable the CPU once all necessary voltage rails are Power Good. The watchdog is configured with a Start Time and a Reset Time. If these times expire and timeout occurs, it means that the CPU providing the WDI signal is not operating. The System Reset signal is then toggled either using a Delay or GPI Tracking Release Delay to determine if the CPU recovers.

UCD90320U sys_reset_watchdog_SLVSCW0.gifFigure 27. System Reset With Watchdog

The default state of the system reset pin (RESET) is assert. When the system reset function is configured in-circuit through PMBus commands during normal operation, the (RESET) pin is briefly asserted by default, even if conditions for de-assert are present. This is because the firmware requires a finite time to examine the de-assert conditions.