SLVSC86A January   2014  – March 2014 UCD9244-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics (Continued)
    7. 7.7  ADC Monitoring Intervals And Response Times
    8. 7.8  Hardware Fault Detection Latency
    9. 7.9  PMBus/SMBus/I2C
    10. 7.10 I2C/SMBus/PMBus Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PMBus Interface
      2. 8.3.2  Resistor Programmed PMBus Address Decode
      3. 8.3.3  VID Interface
      4. 8.3.4  Jtag Interface
      5. 8.3.5  Bias Supply Generator (Shunt Regulator Controller)
      6. 8.3.6  Power-On Reset
      7. 8.3.7  External Reset
      8. 8.3.8  ON_OFF_CONFIG
      9. 8.3.9  Output Voltage Adjustment
      10. 8.3.10 Calibration
      11. 8.3.11 Analog Front End (AFE)
      12. 8.3.12 Voltage Sense Filtering
      13. 8.3.13 DPWM Engine
      14. 8.3.14 Rail/Power Stage Configuration
      15. 8.3.15 DPWM Phase Synchronization
      16. 8.3.16 Output Current Measurement
      17. 8.3.17 Current Sense Input Filtering
      18. 8.3.18 Over-Current Detection
      19. 8.3.19 Input Voltage Monitoring
      20. 8.3.20 Input UV Lockout
      21. 8.3.21 Temperature Monitoring
      22. 8.3.22 Auxiliary ADC Input Monitoring
      23. 8.3.23 Soft Start, Soft Stop Ramp Sequence
      24. 8.3.24 Non-Volatile Memory Error Correction Coding
      25. 8.3.25 Data Logging
    4. 8.4 Device Functional Modes
      1. 8.4.1 4-Bit VID Mode
      2. 8.4.2 6-Bit VID Mode
      3. 8.4.3 8-Bit VID Mode
      4. 8.4.4 Current Foldback Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Automatic System Identification (Auto-ID)
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Digital Compensator
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
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発注情報

8.4.3 8-Bit VID Mode

In 8-bit VID mode, the four VID input signals are not used. Instead, an 8-bit VID code is transmitted to the UCD9244 through the PMBus / I2C port using one of the VID_CODE_RAILn commands, where n is the rail number from 1 to 4.

NAMEDESCRIPTION(1)CODE
VID_CONFIG Selects the VID mode, sets the upper and lower voltage limits, and the starting voltage code at power-up. 0xBB
VID_CODE_RAIL1 Selects the VID code used to set the output voltage for Rail 1. 0xBC
VID_CODE_RAIL2 Selects the VID code used to set the output voltage for Rail 2. 0xBD
VID_CODE_RAIL3 Selects the VID code used to set the output voltage for Rail 3. 0xBE
VID_CODE_RAIL4 Selects the VID code used to set the output voltage for Rail 4. 0xBF
(1) For a complete description of the serial VID commands, see the UCD92xx PMBus Command Reference(SLUU337)
UCD9244-EP VID_codesc_lvsal7.gifFigure 16. PMBus Timing For VID_CODE_RAILn Command

Table 7. Typical PMBus Timing For VID_CODE_RAILn Command at 400kHz

SYMBOLPARAMETERCONDITIONSTYPUNITS
TmsgPEC Message Transmit Time, with PEC 400 kHz clock, PEC enabled 162 – 256 µs
Message Transmit Time, without PEC 400 kHz clock, PEC enabled 126 – 221
Tvo End of message until Vout starts changing 28 – 140 µs
Tmsgvo Start of message until Vout start changing 400 kHz clock, PEC disabled 169 – 314 µs

The total time to transmit the serial VID command will vary depending on the other tasks that the UCD92xx processor is performing. Typical packet times varied from 162 to 256µs when the PMBus is configured for a 400 kb/s transfer rate running and the optional PEC byte is enabled. Disabling the PEC byte saves about 35µs and the transfer times are from 126 to 221µs. Note that these are not specified best-case/worst-case timings, but indicate a range given the typical acknowledge overhead in the host and controller.

After the VID packet has been received by the controller there is a delay before the set-point reference DAC is updated. This delay time varies from ~28µs to 140µs (typical ) depending on the existing priority of updating set-point reference DAC when the command is received.

With a 221µs packet transfer time, it would seem possible to send 4500 VID messages per second to the device. Very short bursts at this rate might be acceptable, but doing so for sustained periods could overwhelm the available processing resources in the UCD92xx, causing it to be delayed in performing its other monitoring and fault response tasks. In addition, if multiple hosts are trying to talk on the PMBus at such high rates then bus contention will occur with great regularity.

To prevent these issues, it is prudent to limit the total VID messaging rate to less than 4 messages per millisecond. In a system with four independent hosts, each host might need to be limited to less than 1 message per millisecond. Therefore, to minimize PMBus traffic, it is best to only issue the VID command when a voltage change is required. There is no benefit to sending the same VID code continuously and repeatedly.