JAJSC47I June   2011  – October 2019 LM5113

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output
      2. 8.3.2 Start-Up and UVLO
      3. 8.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 8.3.4 Level Shift
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VDD Bypass Capacitor
        2. 9.2.2.2 Bootstrap Capacitor
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 サポート・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

6 Pin Configuration and Functions

DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
LM5113 30162901.gif
YFX Package
12-Pin DSBGA
Top View
LM5113 30162902.gif

Pin Functions

PIN TYPE (2) DESCRIPTION
NAME WSON DSBGA
VDD 1 A3, C4(1) P 5-V Positive gate drive supply: locally decouple to VSS using low ESR/ESL capacitor located as close to the IC as possible.
HB 2 D3 P High-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to the IC as possible.
HOH 3 D2 O High-side gate driver turnon output: connect to the gate of high-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnon speed.
HOL 4 D1 O High-side gate driver turnoff output: connect to the gate of high-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnoff speed.
HS 5 C1, D4(1) P High-side GaN FET source connection: connect to the bootstrap capacitor negative terminal and the source of the high-side GaN FET.
HI 6 B4 I High-side driver control input. The LM5113 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open.
LI 7 A4 I Low-side driver control input. The LM5113 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open.
VSS 8 A2 G Ground return: all signals are referenced to this ground.
LOL 9 A1 O Low-side gate driver sink-current output: connect to the gate of the low-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnoff speed.
LOH 10 B1 O Low-side gate driver source-current output: connect to the gate of high-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnon speed.
Exposed Pad EP — — Exposed pad: TI recommends that the exposed pad on the bottom of the package be soldered to ground plane on the printed-circuit board to aid thermal dissipation.
(1) A3 and C4, C1 and D4 are internally connected
(2) I = Input, O = Output, G = Ground, P = Power