JAJSDQ6C June   2012  – September 2017

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Front-End Amplification (Weight-Scale Signal Chain)
    6. 6.6  Electrical Characteristics: Body Composition Measurement Front-End
    7. 6.7  Electrical Characteristics: Analog-to-Digital Converter
    8. 6.8  Electrical Characteristics: Digital Input/Output
    9. 6.9  Timing Requirements: Serial Interface Timing
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Weight-Scale Analog Front-End
        1. 7.3.1.1 Input Common Mode Range
        2. 7.3.1.2 Input Differential Dynamic Range
        3. 7.3.1.3 Offset Correction DAC
          1. 7.3.1.3.1 Offset Correction Example
      2. 7.3.2 Body Composition Measurement Analog Front-End
        1. 7.3.2.1 AC Rectification
        2. 7.3.2.2 I/Q Demodulation
      3. 7.3.3 Digitizer
        1. 7.3.3.1 Multiplexer
        2. 7.3.3.2 Analog-to-Digital Converter
      4. 7.3.4 Reset and Power-Up
      5. 7.3.5 Duty Cycling for Low Power
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 SPI Enable (STE)
        2. 7.5.1.2 Serial Clock (SCLK)
        3. 7.5.1.3 Data Input (SDIN)
        4. 7.5.1.4 Data Output (SDOUT)
        5. 7.5.1.5 Data Ready (RDY)
    6. 7.6 Register Maps
      1. 7.6.1 Register Map
        1. 7.6.1.1  ADC_DATA_RESULT (Address 0x00, Default 0x0000)
        2. 7.6.1.2  ADC_CONTROL_REGISTER1 (Address 0x01, Default 0x01C3)
        3. 7.6.1.3  MISC_REGISTER1 (Address 0x02, Default 0x8000)
        4. 7.6.1.4  MISC_REGISTER2 (Address 0x03, Default 0x7FFF)
        5. 7.6.1.5  DEVICE_CONTROL1 (Address 0x09, Default 0x0000)
        6. 7.6.1.6  ISW_MUX (Address 0x0A, Default 0x0000)
        7. 7.6.1.7  VSENSE_MUX (Address 0x0B, Default 0x0000)
        8. 7.6.1.8  IQ_MODE_ENABLE (Address 0x0C, Default 0x0000)
        9. 7.6.1.9  WEIGHT_SCALE_CONTROL (Address 0x0D, Default 0x0000)
        10. 7.6.1.10 BCM_DAC_FREQ (Address 0x0E, Default 0x0000)
        11. 7.6.1.11 DEVICE_CONTROL2 (Address 0x0F, Default 0x0000)
        12. 7.6.1.12 ADC_CONTROL_REGISTER2 (Address 0x10, Default 0x0000)
        13. 7.6.1.13 MISC_REGISTER3 (Address 0x1A, Default 0x0000)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 BCM Channel Connections
      2. 8.1.2 Handling Oscillation of the Excitation Amplifier
      3. 8.1.3 Achieving Deterministic Phase in the IQ Mode
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Recommendation and Initialization
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

9 Power Supply Recommendations

9.1 Power-Supply Recommendation and Initialization

The device has an analog supply (AVDD). Drive these pins with a clean supply and connect bypass capacitors close to the pins. After power up, the device must be reset to set all internal registers to their default state. Resetting the device is done by applying an active low pulse on the RST pin after the power supplies stabilize. As part of the reset process, the AFE4300 sets all register bits to the respective default settings.

Some register bits must be written to values different from their default values after reset for proper operation. By default, the AFE4300 enters into a power-down state at start-up. The startup and initialization for the device is shown in Figure 16 and Table 6 lists the recommended timing values.

AFE4300 pwrup_sbas586.gif Figure 16. Power-Up and Initialization

Table 6. Timing Parameters for Figure 16

NOM UNIT
t1 Time between supplies turning on and an active RST > 10 ms
t2 Active RST duration > 50 µs
t3 Time between RST and register writes > 1 ms