JAJSDQ6C June   2012  – September 2017

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Front-End Amplification (Weight-Scale Signal Chain)
    6. 6.6  Electrical Characteristics: Body Composition Measurement Front-End
    7. 6.7  Electrical Characteristics: Analog-to-Digital Converter
    8. 6.8  Electrical Characteristics: Digital Input/Output
    9. 6.9  Timing Requirements: Serial Interface Timing
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Weight-Scale Analog Front-End
        1. 7.3.1.1 Input Common Mode Range
        2. 7.3.1.2 Input Differential Dynamic Range
        3. 7.3.1.3 Offset Correction DAC
          1. 7.3.1.3.1 Offset Correction Example
      2. 7.3.2 Body Composition Measurement Analog Front-End
        1. 7.3.2.1 AC Rectification
        2. 7.3.2.2 I/Q Demodulation
      3. 7.3.3 Digitizer
        1. 7.3.3.1 Multiplexer
        2. 7.3.3.2 Analog-to-Digital Converter
      4. 7.3.4 Reset and Power-Up
      5. 7.3.5 Duty Cycling for Low Power
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 SPI Enable (STE)
        2. 7.5.1.2 Serial Clock (SCLK)
        3. 7.5.1.3 Data Input (SDIN)
        4. 7.5.1.4 Data Output (SDOUT)
        5. 7.5.1.5 Data Ready (RDY)
    6. 7.6 Register Maps
      1. 7.6.1 Register Map
        1. 7.6.1.1  ADC_DATA_RESULT (Address 0x00, Default 0x0000)
        2. 7.6.1.2  ADC_CONTROL_REGISTER1 (Address 0x01, Default 0x01C3)
        3. 7.6.1.3  MISC_REGISTER1 (Address 0x02, Default 0x8000)
        4. 7.6.1.4  MISC_REGISTER2 (Address 0x03, Default 0x7FFF)
        5. 7.6.1.5  DEVICE_CONTROL1 (Address 0x09, Default 0x0000)
        6. 7.6.1.6  ISW_MUX (Address 0x0A, Default 0x0000)
        7. 7.6.1.7  VSENSE_MUX (Address 0x0B, Default 0x0000)
        8. 7.6.1.8  IQ_MODE_ENABLE (Address 0x0C, Default 0x0000)
        9. 7.6.1.9  WEIGHT_SCALE_CONTROL (Address 0x0D, Default 0x0000)
        10. 7.6.1.10 BCM_DAC_FREQ (Address 0x0E, Default 0x0000)
        11. 7.6.1.11 DEVICE_CONTROL2 (Address 0x0F, Default 0x0000)
        12. 7.6.1.12 ADC_CONTROL_REGISTER2 (Address 0x10, Default 0x0000)
        13. 7.6.1.13 MISC_REGISTER3 (Address 0x1A, Default 0x0000)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 BCM Channel Connections
      2. 8.1.2 Handling Oscillation of the Excitation Amplifier
      3. 8.1.3 Achieving Deterministic Phase in the IQ Mode
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Recommendation and Initialization
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage range AVDD to AVSS –0.3 4.1 V
Any pin –0.3 AVDD + 0.3
Diode current at any device pin ±2 mA
Maximum operating junction temperature, TJ max 105 °C
Storage humidity 10% 90% Rh
Storage temperature, Tstg –25 85 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Supply voltage 2 3.6 V
AVSS Ground 0 V
fCLK External clock input frequency 1 MHz
TA Ambient temperature range 0 70 °C

6.4 Thermal Information

THERMAL METRIC(1) AFE4300 UNIT
PN (LQFP)
80 PINS
RθJA Junction-to-ambient thermal resistance 50.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.2 °C/W
RθJB Junction-to-board thermal resistance 25.3 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 24.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: Front-End Amplification (Weight-Scale Signal Chain)

over operating free-air temperature range, AVDD – AVSS = 3 V, G1 = 183, and G2 = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS AFE4300 UNIT
MIN TYP MAX
BRIDGE SUPPLY
V(VLDO) Output voltage (bridge supply voltage) 1.7 V
IO Output current Current capability 20 mA
Short-circuit protection 100 mA
tSTBY Enable, disable time With 470-nF capacitor on the VLDO pin 1 ms
AMPLIFICATION CHAIN
Offset error With offset correction DAC disabled 80 µV
Offset drift vs temperature With offset correction DAC disabled 0.25 µV/°C
Input bias current ±70 fA
Input offset current ±140 fA
Vn Noise voltage, equivalent input G1 = 183, 0.01 Hz < f < 2 Hz 68 nVrms
In Noise current, equivalent input f = 10 Hz 100 fA/√Hz
zid Differential input impedance 100 || 4 GΩ || pF
zic Common-mode input impedance 100 || 8 GΩ || pF
CMRR Input common-mode rejection ratio G1 = 183 95 dB
INLWS Gain nonlinearity From input to digital output
(including ADC)		 0.01 % of FS(1)
First-stage gain equation (1 + 2 × 100k / RG) V/V
tup Power-up time From power up to valid reading 1 ms
RFB1 Internal feedback resistors 95 100 105 kΩ
Gain2 Second-stage gain settings 1, 2, 3, 4
Total gain error ±5%
Offset DAC number of bits 6 Bits
IDAC Full-scale offset DAC output current ±6.5 µA
(1) FS = full-scale.

6.6 Electrical Characteristics: Body Composition Measurement Front-End

over operating free-air temperature range, AVDD – AVSSS = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS AFE4300 UNIT
MIN TYP MAX
WAVEFORM GENERATOR
DAC resolution 6 Bits
DAC full-scale voltage Common-mode voltage = 0.9 V 1.05 V(PP)
DAC sample rate 1 MSPS
BWLPF –3 dB bandwidth of the 2nd-order low-pass filter 150 ±30 kHz
R1 Internal current-setting resistor 1.5 ±20% kΩ
DEMODULATION CHAIN
Input Impedance 50 kΩ
Gain From impedance to dc output of demodulator, IQ mode and FWR mode 0.72 V/kΩ
Gain error (without calibration) FWR mode and I/Q mode 2.5 % of FS
Offset error (without calibration) FWR mode and I/Q mode ±5 mV
CMRR Common-mode rejection ratio 75 dB
Nonlinearity 0-Ω to 1.25-kΩ range 0.15 % of FS
0-Ω to 2.50-kΩ range 3 % of FS
BWDEMOD Rectifier bandwidth Internal resistor = 5 kΩ,
external capacitor = 4.7 µF		 3.5 ±20% Hz
Output noise at rectifier output 20-kHz waveform, noise integrated from 0.01 Hz to 2 Hz 15 µVrms

6.7 Electrical Characteristics: Analog-to-Digital Converter

over operating free-air temperature range, AVDD – AVSS = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS AFE4300 UNIT
MIN TYP MAX
ANALOG-TO-DIGITAL CONVERTER
ADC input voltage range At the input of the ADC (after PGA) 2 × VREF V
VIN Full-scale input voltage At the input of the PGA VADC / Gain V
VREF Reference voltage 1.7 V
RON(mux) Input multiplexer on-resistance 0 V ≤ VAAUX ≤ AVDD 6 kΩ
AAUX input impedance 4 MΩ
fDR Output data rate 8 860 SPS
Resolution 16 Bits
EI Integral linearity error Best fit, DR = 8 SPS 1 LSB
EO Offset error Differential inputs ±1 LSB
Single-ended inputs ±3 LSB
EG Gain error 0.05%
VBAT_MON Battery monitor output AVDD / 3 V
IBAT_MON Battery monitor current consumption 1.5 µA
IBAT_MON_ACC Battery monitor accuracy ±2%
POWER CONSUMPTION
Supply current Power-down current 0.25 µA
Sleep-mode current 100 µA
Weight-scale chain measurements 540 µA
Body-composition measurements 970 µA
Auxillary-channel measurements 110 µA

6.8 Electrical Characteristics: Digital Input/Output

over operating free-air temperature range, AVDD – AVSS = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 0.75 × AVDD AVDD V
VIL Low-level input voltage AVSS 0.25 × AVDD V
VOH High-level output voltage IOL = 1 mA 0.8 × AVDD V
VOL Low-level output voltage IOL = 1 mA GND 0.2 × AVDD V
IIN Input current ±30 µA

6.9 Timing Requirements: Serial Interface Timing

at TA = 0°C to +70°C and VDD = 2 V to 3.6 V (unless otherwise noted)
MIN NOM MAX UNIT
tCSSC STE low to first SCLK setup time(1) 100 ns
tSCLK SCLK period 250 ns
tSPWH SCLK pulse duration high 100 ns
tSPWL SCLK pulse duration low 100 ns
tDIST Valid SDIN to SCLK falling edge setup time 50 ns
tDIHD Valid SDIN to SCLK falling edge hold time 50 ns
tDOPD SCLK rising edge to valid new SDOUT propagation delay(2) 50 ns
tDOHD SCLK rising edge to DOUT invalid hold time 0 ns
tCSDOD STE low to SDOUT driven propagation delay 100 ns
tCSDOZ STE high to SDOUT Hi-Z propagation delay 100 ns
tCSH STE high pulse 200 ns
tSCCS Final SCLK falling edge to STE high 100 ns
(1) STE can be tied low.
(2) DOUT load = 20 pF || 100 kΩ to DGND.
AFE4300 tim_serial_bas586.gif Figure 1. Serial Interface Timing

6.10 Typical Characteristics

all measurements at room temperature with AVDD = 3 V (unless otherwise specified)
AFE4300 G001_SBAS586.png
Figure 2. Weight-Scale Chain Noise vs Frequency
AFE4300 G005_SBAS586.gif
Figure 4. BCM DAC Output Current Distribution
AFE4300 G004_SBAS586.png
Figure 3. Weight-Scale Chain Nonlinearity
AFE4300 G006_SBAS586.png
Figure 5. Body Impedance to Output Voltage Transfer Curve