JAJSEJ0E January   2018  – April 2019 TS5MP646

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      D-PHYの概略回路図
      2.      C-PHYの概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powered-Off Protection
      2. 8.3.2 1.8-V Logic Compatible Inputs
      3. 8.3.3 Low Power Disable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
      2. 8.4.2 Low Power Disable Mode
      3. 8.4.3 Switch Enabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 MIPI D-PHY Application
        2. 9.2.3.2 MIPI C-PHY Application
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.3.1 Powered-Off Protection

When the TS5MP646 is powered off (VDD = 0 V) the I/Os and digital logic pins of the device remains in a high impedance state. The crosstalk, off-isolation, and leakage will remain within the electrical specifications. This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is powering up.

Figure 20 shows an example system containing a switch without powered-off protection with the following system level scenario.

  1. Subsystem A powers up and starts sending information to Subsystem B that remains unpowered.
  2. The I/O voltage back powers the supply rail in Subsystem B.
  3. The digital logic is back powered and turns on the switch. The signal is transmitted to Subsystem B before it is powered and damages it.

TS5MP646 scds371-PoP-1.gifFigure 20. System Without Powered-Off Protection

With powered-off protection, the switch prevents back powering the supply and the switch remains high-impedance. Subsystem B remains protected.

TS5MP646 scds371-PoP-2.gifFigure 21. System With Powered-Off Protection

This features has the following system level benefits.

  • Protects the system from damage.
  • Prevents data from being transmitted unintentionally
  • Eliminates the need for power sequencing solutions reducing BOM count and cost, simplifying system design and improving reliability.