10.5.9 Default Device Configurations in EEPROM and ROM
Table 10 through Table 13 show the device default configurations stored in the on-chip EEPROM. Table 14 through Table 18 show the device default configurations stored in the on-chip ROM.
Table 10. Default EEPROM Contents (HW_SW_CTRL = 0) – Input and Status Configuration(1)(2)
GPIO [3:2] |
PRI INPUT (MHz) |
PRI TYPE |
PRI DOUBLER |
SEC INPUT (MHz) |
SEC TYPE |
XO INT LOAD (pF) |
SEC DOUBLER |
STATUS1 MUX |
STATUS0 MUX |
PREDIV |
DIV |
STATUS1 / STATUS0 FREQ (MHz) |
STATUS1 / STATUS0 RISE / FALL TIME (ns) |
VIM, VIM
|
25 |
DIFF |
Enabled |
25 |
XTAL |
9 |
Enabled |
LOL |
Disable |
n/a |
n/a |
n/a |
n/a |
00 |
25 |
DIFF |
Enabled |
25 |
XTAL |
9 |
Enabled |
LOL |
PLL |
4 |
25 |
n/a / 50 |
n/a / 2.1 |
01 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
LOL |
PLL |
4 |
25 |
n/a / 50 |
n/a / 2.1 |
(1) 100-Ω internal termination enabled (if applicable)
(2) Internal AC biasing enabled (if applicable)
Table 11. Default EEPROM Contents (HW_SW_CTRL = 0) – PLL Configuration(1)
GPIO [3:2] |
PLL INPUT MUX |
PLL INPUT (MHz) |
PLL TYPE |
PLL R DIV |
PLL M DIV |
PLL N DIV |
PLL N DIV INT |
PLL N DIV NUM |
PLL N DIV DEN |
PLL FRAC ORDER |
PLL FRAC DITHER |
PLL VCO (MHz) |
PLL P DIV |
VIM, VIM
|
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
102 |
102 |
0 |
1 |
n/a |
Disabled |
5100 |
8 |
00 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
4000000 |
n/a |
Disabled |
5000 |
2 |
01 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
4000000 |
n/a |
Disabled |
5000 |
2 |
(1) When PLL is set as an integer-based clock generator, external loop filter component, C2, should be 3.3 nF and loop bandwidth is around 400 kHz. When PLL is set as a fractional-based clock generator, external loop filter component, C2, should be 33 nF and loop bandwidth is around 400 kHz.
Table 12. Default EEPROM Contents (HW_SW_CTRL = 0) – Outputs [0-3] Configuration
GPIO [3:2] |
OUT0-1 DIVIDER |
OUT0-1 FREQ (MHz) |
OUT0 TYPE |
OUT1 TYPE |
OUT2-3 DIVIDER |
OUT2-3 FREQ (MHz) |
OUT2 TYPE |
OUT3 TYPE |
VIM, VIM
|
n/a |
n/a |
Disable |
Disable |
n/a |
n/a |
Disable |
Disable |
00 |
25 |
100 |
LVPECL |
LVCMOS (+/-) |
25 |
100 |
LVCMOS (+/-) |
LVCMOS (+/-) |
01 |
25 |
100 |
LVCMOS (+/-) |
LVCMOS (+/-) |
25 |
100 |
LVCMOS (+/-) |
LVCMOS (+/-) |
Table 13. Default EEPROM Contents (HW_SW_CTRL = 0) – Outputs [4-7] Configuration
GPIO [3:2] |
OUT4 DIV |
OUT4 FREQ (MHz) |
OUT4 MUX SELECT |
OUT4 TYPE |
OUT5 DIV |
OUT5 FREQ (MHz) |
OUT5 MUX SELECT |
OUT5 TYPE |
OUT6 DIV |
OUT6 FREQ (MHz) |
OUT6 MUX SELECT |
OUT6 TYPE |
OUT7 DIV |
OUT7 FREQ (MHz) |
OUT7 MUX SELECT |
OUT7 TYPE |
VIM, VIM
|
3 |
212.5 |
PLL |
LVPECL |
3 |
212.5 |
PLL |
LVPECL |
6 |
106.25 |
PLL |
LVPECL |
6 |
106.25 |
PLL |
LVPECL |
00 |
16 |
156.25 |
PLL |
LVPECL |
20 |
125 |
PLL |
LVPECL |
20 |
125 |
PLL |
LVDS |
100 |
25 |
PLL |
LVPECL |
01 |
25 |
100 |
PLL |
LVCMOS (+/-) |
20 |
125 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
Table 14. Default ROM Contents (HW_SW_CTRL = 1) - Input Configuration
GPIO[5:0] (decimal) |
PRI INPUT (MHz) |
PRI TYPE |
PRI DOUBLER |
SEC INPUT (MHz) |
SEC TYPE |
XO INT LOAD (pF) |
SEC DOUBLER |
0 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
1 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
2 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
3 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
4 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
5 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
6 |
30.72 |
LVCMOS |
Disabled |
30.72 |
XTAL |
9 |
Disabled |
7 |
19.2 |
LVCMOS |
Disabled |
19.2 |
XTAL |
9 |
Disabled |
8 |
10 |
LVCMOS |
Disabled |
10 |
XTAL |
9 |
Disabled |
9 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
10 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
11 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
12 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
13 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
14 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
15 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
16 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
17 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
18 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
19 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
20 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
21 |
19.44 |
LVCMOS |
Disabled |
19.44 |
XTAL |
9 |
Disabled |
22 |
38.88 |
LVCMOS |
Disabled |
38.88 |
XTAL |
9 |
Disabled |
23 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
24 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
25 |
19.44 |
LVCMOS |
Disabled |
19.44 |
XTAL |
9 |
Disabled |
26 |
38.88 |
LVCMOS |
Disabled |
38.88 |
XTAL |
9 |
Disabled |
27 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
n/a |
Enabled |
28 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
n/a |
Enabled |
29 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
30 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
31 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
n/a |
Enabled |
32 |
25 |
LVCMOS |
Enabled |
25 |
LVCMOS |
n/a |
Enabled |
33 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
34 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
35 |
19.44 |
LVCMOS |
Disabled |
19.44 |
XTAL |
9 |
Disabled |
36 |
38.88 |
LVCMOS |
Disabled |
38.88 |
XTAL |
9 |
Disabled |
37 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
38 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
39 |
19.44 |
LVCMOS |
Disabled |
19.44 |
XTAL |
9 |
Disabled |
40 |
38.88 |
LVCMOS |
Disabled |
38.88 |
XTAL |
9 |
Disabled |
41 |
19.44 |
LVCMOS |
Disabled |
19.44 |
XTAL |
9 |
Disabled |
42 |
38.88 |
LVCMOS |
Disabled |
38.88 |
XTAL |
9 |
Disabled |
43 |
19.44 |
LVCMOS |
Disabled |
19.44 |
XTAL |
9 |
Disabled |
44 |
38.88 |
LVCMOS |
Disabled |
38.88 |
XTAL |
9 |
Disabled |
45 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
46 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
47 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
48 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
49 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
50 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
51 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
52 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
53 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
54 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
55 |
19.44 |
LVCMOS |
Disabled |
19.44 |
XTAL |
9 |
Disabled |
56 |
38.88 |
LVCMOS |
Disabled |
38.88 |
XTAL |
9 |
Disabled |
57 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
58 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
59 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
60 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
61 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
62 |
50 |
LVCMOS |
Enabled |
50 |
XTAL |
9 |
Enabled |
63 |
25 |
LVCMOS |
Enabled |
25 |
XTAL |
9 |
Enabled |
Table 15. Default ROM Contents (HW_SW_CTRL = 1) - Status Configuration
GPIO[5:0] (decimal) |
STATUS1 MUX |
STATUS0 MUX |
STATUS1 PREDIV |
STATUS1 DIV |
STATUS1 FREQ (MHz) |
STATUS1 RISE/FALL TIME (ns) |
STATUS0 PREDIV |
STATUS0 DIV |
STATUS0 FREQ (MHz) |
STATUS0 RISE/FALL TIME (ns) |
0 |
LOL |
PLL |
n/a |
n/a |
n/a |
n/a |
5 |
20 |
50 |
2.1 |
1 |
LOL |
PLL |
n/a |
n/a |
n/a |
n/a |
5 |
40 |
25 |
2.1 |
2 |
LOL |
LOR_PRI |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
3 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
4 |
LOL |
LOR_PRI |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
5 |
PLL |
PLL |
5 |
40 |
25 |
2.1 |
5 |
40 |
25 |
2.1 |
6 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
7 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
8 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
9 |
PLL |
LOL |
4 |
51 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
10 |
PLL |
LOL |
4 |
51 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
11 |
PLL |
LOL |
5 |
30 |
33.3333 |
2.1 |
n/a |
n/a |
n/a |
n/a |
12 |
PLL |
LOL |
5 |
30 |
33.3333 |
2.1 |
n/a |
n/a |
n/a |
n/a |
13 |
PLL |
LOL |
4 |
51 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
14 |
PLL |
LOL |
4 |
51 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
15 |
PLL |
LOL |
4 |
51 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
16 |
PLL |
LOL |
4 |
51 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
17 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
18 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
19 |
PLL |
LOL |
5 |
40 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
20 |
PLL |
LOL |
5 |
40 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
21 |
PLL |
LOL |
5 |
40 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
22 |
PLL |
LOL |
5 |
40 |
25 |
2.1 |
n/a |
n/a |
n/a |
n/a |
23 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
24 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
25 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
26 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
27 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
28 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
29 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
30 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
31 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
32 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
33 |
PLL |
LOL |
5 |
15 |
66.6666 |
2.1 |
n/a |
n/a |
n/a |
n/a |
34 |
PLL |
LOL |
5 |
15 |
66.6666 |
2.1 |
n/a |
n/a |
n/a |
n/a |
35 |
PLL |
LOL |
5 |
15 |
66.6666 |
2.1 |
n/a |
n/a |
n/a |
n/a |
36 |
PLL |
LOL |
5 |
15 |
66.6666 |
2.1 |
n/a |
n/a |
n/a |
n/a |
37 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
38 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
39 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
40 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
41 |
PLL |
LOL |
4 |
32 |
38.88 |
2.1 |
n/a |
n/a |
n/a |
n/a |
42 |
PLL |
LOL |
4 |
32 |
38.88 |
2.1 |
n/a |
n/a |
n/a |
n/a |
43 |
PLL |
LOL |
4 |
32 |
38.88 |
2.1 |
n/a |
n/a |
n/a |
n/a |
44 |
PLL |
LOL |
4 |
32 |
38.88 |
2.1 |
n/a |
n/a |
n/a |
n/a |
45 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
46 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
47 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
48 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
49 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
50 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
51 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
52 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
53 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
54 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
55 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
56 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
57 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
58 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
59 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
60 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
61 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
62 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
63 |
LOR_PRI |
LOL |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
n/a |
Table 16. Default ROM Contents (HW_SW_CTRL = 1) – PLL Configuration(1)
GPIO[5:0] (decimal) |
PLL IN MUX |
PLL IN (MHz) |
PLL TYPE |
PLL R DIV |
PLL M DIV |
PLL N DIV |
PLL N DIV INT |
PLL N DIV NUM |
PLL N DIV DEN |
PLL FRAC ORDER |
PLL FRAC DITHER |
PLL VCO (MHz) |
PLL P DIV |
0 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
5 |
1 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
5 |
2 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
5 |
3 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
4 |
4 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
5 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
6 |
REFSEL |
30.72 |
Jitter Cleaner Integer |
1 |
24 |
3840 |
3840 |
0 |
1 |
n/a |
Disabled |
4915.2 |
4 |
7 |
REFSEL |
19.2 |
Clock Gen Integer |
1 |
1 |
256 |
256 |
0 |
1 |
n/a |
Disabled |
4915.2 |
4 |
8 |
REFSEL |
10 |
Clock Gen Integer |
1 |
1 |
491.52 |
491 |
1300000 |
2500000 |
Third |
Enabled |
4915.2 |
4 |
9 |
REFSEL |
25 |
Clock Gen Fractional |
1 |
1 |
102 |
102 |
0 |
1 |
n/a |
Disabled |
5100 |
8 |
10 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
51 |
51 |
0 |
1 |
n/a |
Disabled |
5100 |
8 |
11 |
REFSEL |
25 |
Clock Gen Fractional |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
12 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
13 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
102 |
102 |
0 |
1 |
n/a |
Disabled |
5100 |
3 |
14 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
51 |
51 |
0 |
1 |
n/a |
Disabled |
5100 |
3 |
15 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
102 |
102 |
0 |
1 |
n/a |
Disabled |
5100 |
3 |
16 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
51 |
51 |
0 |
1 |
n/a |
Disabled |
5100 |
3 |
17 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
18 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
19 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
20 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
21 |
REFSEL |
19.44 |
Clock Gen Integer |
1 |
1 |
257.2016461 |
257 |
157536 |
781250 |
Third |
Enabled |
5000 |
8 |
22 |
REFSEL |
38.88 |
Clock Gen Integer |
1 |
1 |
128.600823 |
128 |
469393 |
781250 |
Third |
Enabled |
5000 |
8 |
23 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
24 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
25 |
REFSEL |
19.44 |
Clock Gen Integer |
1 |
1 |
257.2016461 |
257 |
157536 |
781250 |
Third |
Enabled |
5000 |
2 |
26 |
REFSEL |
38.88 |
Clock Gen Integer |
1 |
1 |
128.600823 |
128 |
469393 |
781250 |
Third |
Enabled |
5000 |
2 |
27 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
28 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
29 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
30 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
31 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
32 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
33 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
34 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
35 |
REFSEL |
19.44 |
Clock Gen Integer |
1 |
1 |
257.2016461 |
257 |
157536 |
781250 |
Third |
Enabled |
5000 |
8 |
36 |
REFSEL |
38.88 |
Clock Gen Fractional |
1 |
1 |
128.600823 |
128 |
469393 |
781250 |
Third |
Enabled |
5000 |
8 |
37 |
REFSEL |
25 |
Clock Gen Fractional |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
38 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
39 |
REFSEL |
19.44 |
Clock Gen Integer |
1 |
1 |
257.2016461 |
257 |
157536 |
781250 |
Third |
Enabled |
5000 |
8 |
40 |
REFSEL |
38.88 |
Clock Gen Fractional |
1 |
1 |
128.600823 |
128 |
469393 |
781250 |
Third |
Enabled |
5000 |
8 |
41 |
REFSEL |
19.44 |
Clock Gen Integer |
1 |
1 |
256 |
256 |
0 |
1 |
n/a |
Disabled |
4976.64 |
8 |
42 |
REFSEL |
38.88 |
Clock Gen Fractional |
1 |
1 |
128 |
128 |
0 |
1 |
n/a |
Disabled |
4976.64 |
8 |
43 |
REFSEL |
19.44 |
Clock Gen Integer |
1 |
1 |
256 |
256 |
0 |
1 |
n/a |
Disabled |
4976.64 |
8 |
44 |
REFSEL |
38.88 |
Clock Gen Fractional |
1 |
1 |
128 |
128 |
0 |
1 |
n/a |
Disabled |
4976.64 |
8 |
45 |
REFSEL |
25 |
Clock Gen Fractional |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
5 |
46 |
REFSEL |
50 |
Clock Gen Fractional |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
5 |
47 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
48 |
REFSEL |
50 |
Clock Gen Fractional |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
49 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
50 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
51 |
REFSEL |
25 |
Clock Gen Fractional |
1 |
1 |
106.25 |
106 |
1000000 |
4000000 |
First |
Enabled |
5312.5 |
2 |
52 |
REFSEL |
50 |
Clock Gen Fractional |
1 |
1 |
53.125 |
53 |
500000 |
4000000 |
First |
Enabled |
5312.5 |
2 |
53 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
103.125 |
103 |
500000 |
4000000 |
First |
Enabled |
5156.25 |
8 |
54 |
REFSEL |
50 |
Clock Gen Fractional |
1 |
1 |
51.5625 |
51 |
2250000 |
4000000 |
First |
Enabled |
5156.25 |
8 |
55 |
REFSEL |
19.44 |
Clock Gen Fractional |
1 |
1 |
265.2391976 |
265 |
597994 |
2500000 |
Third |
Enabled |
5156.25 |
8 |
56 |
REFSEL |
38.88 |
Clock Gen Integer |
1 |
1 |
132.6195988 |
132 |
1548997 |
2500000 |
Third |
Enabled |
5156.25 |
8 |
57 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
58 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
2 |
59 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
60 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
61 |
REFSEL |
25 |
Clock Gen Integer |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
62 |
REFSEL |
50 |
Clock Gen Integer |
1 |
1 |
50 |
50 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
63 |
REFSEL |
25 |
Clock Gen Fractional |
1 |
1 |
100 |
100 |
0 |
1 |
n/a |
Disabled |
5000 |
8 |
(1) When PLL is set as an integer-based clock generator, external loop filter component, C2, should be 3.3nF and loop bandwidth is around 400kHz. When PLL is set as a fractional-based clock generator, external loop filter component, C2, should be 33nF and loop bandwidth is around 400kHz.
Table 17. Default ROM Contents (HW_SW_CTRL = 1) - Outputs [0-4] Configuration
GPIO[5:0] (decimal) |
OUT0-1 DIVIDER |
OUT0-1 FREQ (MHz) |
OUT0 TYPE |
OUT1 TYPE |
OUT2-3 DIVIDER |
OUT2-3 FREQ (MHz) |
OUT2 TYPE |
OUT3 TYPE |
OUT4 DIV |
OUT4 FREQ (MHz) |
OUT4 MUX SELECT |
OUT4 TYPE |
0 |
5 |
200 |
LVDS |
LVDS |
10 |
100 |
LVDS |
LVDS |
1 |
n/a |
n/a |
Disable |
1 |
5 |
200 |
LVDS |
LVDS |
10 |
100 |
LVDS |
LVDS |
1 |
n/a |
n/a |
Disable |
2 |
10 |
100 |
LVDS |
LVDS |
10 |
100 |
LVDS |
LVDS |
8 |
125 |
PLL |
LVDS |
3 |
4 |
312.5 |
LVDS |
LVDS |
8 |
156.25 |
LVPECL |
LVPECL |
10 |
125 |
PLL |
LVDS |
4 |
20 |
125 |
LVPECL |
LVPECL |
16 |
156.25 |
LVPECL |
LVPECL |
25 |
100 |
PLL |
LVPECL |
5 |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
PLL |
LVPECL |
6 |
4 |
307.2 |
LVPECL |
LVPECL |
5 |
245.76 |
LVDS |
LVDS |
8 |
153.6 |
PLL |
LVDS |
7 |
4 |
307.2 |
LVPECL |
LVPECL |
5 |
245.76 |
LVPECL |
LVPECL |
8 |
153.6 |
PLL |
LVDS |
8 |
4 |
307.2 |
LVPECL |
LVPECL |
5 |
245.76 |
LVDS |
LVDS |
8 |
153.6 |
PLL |
LVDS |
9 |
6 |
106.25 |
LVPECL |
LVPECL |
6 |
106.25 |
LVPECL |
LVPECL |
3 |
212.5 |
PLL |
LVPECL |
10 |
6 |
106.25 |
LVDS |
LVDS |
6 |
106.25 |
LVDS |
LVDS |
3 |
212.5 |
PLL |
LVDS |
11 |
16 |
156.25 |
LVPECL |
LVPECL |
20 |
125 |
LVPECL |
LVPECL |
25 |
100 |
PLL |
HCSL |
12 |
16 |
156.25 |
LVDS |
LVDS |
20 |
125 |
LVDS |
LVDS |
25 |
100 |
PLL |
HCSL |
13 |
16 |
106.25 |
LVPECL |
LVPECL |
16 |
106.25 |
LVPECL |
LVPECL |
17 |
100 |
PLL |
HCSL |
14 |
16 |
106.25 |
LVDS |
LVDS |
16 |
106.25 |
LVDS |
LVDS |
17 |
100 |
PLL |
HCSL |
15 |
4 |
425 |
LVPECL |
LVPECL |
8 |
212.5 |
LVPECL |
LVPECL |
17 |
100 |
PLL |
HCSL |
16 |
4 |
425 |
LVDS |
LVDS |
8 |
212.5 |
LVDS |
LVDS |
17 |
100 |
PLL |
HCSL |
17 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
18 |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
PLL |
LVDS |
19 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
20 |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
PLL |
LVDS |
21 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
22 |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
PLL |
LVDS |
23 |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
LVPECL |
LVPECL |
25 |
100 |
PLL |
LVDS |
24 |
16 |
156.25 |
LVDS |
LVDS |
16 |
156.25 |
LVDS |
LVDS |
25 |
100 |
PLL |
LVDS |
25 |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
LVPECL |
LVPECL |
25 |
100 |
PLL |
LVDS |
26 |
16 |
156.25 |
LVDS |
LVDS |
16 |
156.25 |
LVDS |
LVDS |
25 |
100 |
PLL |
LVDS |
27 |
16 |
156.25 |
LVPECL |
LVPECL |
25 |
100 |
LVPECL |
LVPECL |
50 |
50 |
PLL |
LVPECL |
28 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
29 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
30 |
8 |
312.5 |
LVDS |
LVDS |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
PLL |
LVDS |
31 |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
PLL |
LVPECL |
32 |
4 |
625 |
LVDS |
LVDS |
4 |
625 |
LVPECL |
LVPECL |
25 |
100 |
PLL |
LVDS |
33 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
34 |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVDS |
35 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
36 |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVDS |
37 |
4 |
156.25 |
LVPECL |
LVPECL |
5 |
125 |
LVDS |
LVDS |
5 |
125 |
PLL |
LVDS |
38 |
4 |
156.25 |
LVDS |
LVDS |
5 |
125 |
LVDS |
LVDS |
5 |
125 |
PLL |
LVDS |
39 |
4 |
156.25 |
LVPECL |
LVPECL |
5 |
125 |
HCSL |
HCSL |
5 |
125 |
PLL |
LVDS |
40 |
4 |
156.25 |
LVDS |
LVDS |
5 |
125 |
LVDS |
LVDS |
5 |
125 |
PLL |
LVDS |
41 |
2 |
311.04 |
LVPECL |
LVPECL |
4 |
155.52 |
LVDS |
LVDS |
4 |
155.52 |
PLL |
LVPECL |
42 |
2 |
311.04 |
LVDS |
LVDS |
4 |
155.52 |
LVPECL |
LVPECL |
4 |
155.52 |
PLL |
LVDS |
43 |
1 |
622.08 |
LVPECL |
LVPECL |
1 |
622.08 |
LVPECL |
LVPECL |
4 |
155.52 |
PLL |
LVDS |
44 |
1 |
622.08 |
LVDS |
LVDS |
1 |
622.08 |
LVPECL |
LVPECL |
4 |
155.52 |
PLL |
LVDS |
45 |
10 |
100 |
LVPECL |
LVPECL |
10 |
100 |
LVPECL |
LVPECL |
4 |
250 |
PLL |
LVPECL |
46 |
10 |
100 |
LVDS |
LVDS |
10 |
100 |
LVPECL |
LVPECL |
4 |
250 |
PLL |
LVDS |
47 |
25 |
25 |
LVPECL |
LVPECL |
2 |
312.5 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
48 |
25 |
25 |
LVDS |
LVDS |
2 |
312.5 |
LVDS |
LVDS |
4 |
156.25 |
PLL |
LVDS |
49 |
25 |
25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
50 |
25 |
25 |
LVDS |
LVDS |
4 |
156.25 |
LVDS |
LVDS |
4 |
156.25 |
PLL |
LVDS |
51 |
25 |
106.25 |
LVPECL |
LVPECL |
25 |
106.25 |
LVPECL |
LVPECL |
17 |
156.25 |
PLL |
LVPECL |
52 |
25 |
106.25 |
LVDS |
LVDS |
25 |
106.25 |
LVDS |
LVDS |
17 |
156.25 |
PLL |
LVDS |
53 |
4 |
161.1328125 |
LVPECL |
LVPECL |
4 |
161.1328125 |
LVPECL |
LVPECL |
2 |
322.265625 |
PLL |
LVPECL |
54 |
4 |
161.1328125 |
LVDS |
LVDS |
4 |
161.1328125 |
LVPECL |
LVPECL |
2 |
322.265625 |
PLL |
LVDS |
55 |
4 |
161.1328125 |
LVPECL |
LVPECL |
4 |
161.1328125 |
LVPECL |
LVPECL |
2 |
322.265625 |
PLL |
LVPECL |
56 |
4 |
161.1328125 |
LVDS |
LVDS |
4 |
161.1328125 |
LVPECL |
LVPECL |
2 |
322.265625 |
PLL |
LVDS |
57 |
16 |
156.25 |
LVPECL |
LVPECL |
16 |
156.25 |
LVPECL |
LVPECL |
25 |
100 |
PLL |
HCSL |
58 |
16 |
156.25 |
LVDS |
LVDS |
16 |
156.25 |
LVDS |
LVDS |
25 |
100 |
PLL |
HCSL |
59 |
2 |
312.5 |
LVPECL |
LVPECL |
2 |
312.5 |
LVPECL |
LVPECL |
2 |
312.5 |
PLL |
LVPECL |
60 |
2 |
312.5 |
LVPECL |
LVPECL |
2 |
312.5 |
LVPECL |
LVPECL |
2 |
312.5 |
PLL |
LVPECL |
61 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
62 |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
LVPECL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
63 |
5 |
125 |
LVPECL |
LVPECL |
5 |
125 |
LVPECL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
Table 18. Default ROM Contents (HW_SW_CTRL = 1) - Outputs [5-7] Configuration
GPIO[5:0] (decimal) |
OUT5 DIV |
OUT5 FREQ (MHz) |
OUT5 MUX SELECT |
OUT5 TYPE |
OUT6 DIV |
OUT6 FREQ (MHz) |
OUT6 MUX SELECT |
OUT6 TYPE |
OUT7 DIV |
OUT7 FREQ (MHz) |
OUT7 MUX SELECT |
OUT7 TYPE |
0 |
1 |
n/a |
n/a |
Disable |
1 |
n/a |
n/a |
Disable |
1 |
n/a |
n/a |
Disable |
1 |
1 |
n/a |
n/a |
Disable |
1 |
n/a |
n/a |
Disable |
1 |
n/a |
n/a |
Disable |
2 |
8 |
125 |
PLL |
LVDS |
8 |
125 |
PLL |
LVDS |
8 |
125 |
PLL |
LVDS |
3 |
10 |
125 |
PLL |
LVDS |
25 |
50 |
PLL |
LVDS |
25 |
50 |
PLL |
LVDS |
4 |
20 |
125 |
PLL |
LVPECL |
16 |
156.25 |
PLL |
LVPECL |
16 |
156.25 |
PLL |
LVPECL |
5 |
20 |
125 |
PLL |
LVPECL |
20 |
125 |
PLL |
LVPECL |
20 |
125 |
PLL |
LVPECL |
6 |
8 |
153.6 |
PLL |
LVDS |
10 |
122.88 |
PLL |
LVDS |
10 |
122.88 |
PLL |
LVDS |
7 |
8 |
153.6 |
PLL |
LVDS |
10 |
122.88 |
PLL |
LVDS |
10 |
122.88 |
PLL |
LVDS |
8 |
8 |
153.6 |
PLL |
LVDS |
10 |
122.88 |
PLL |
LVDS |
10 |
122.88 |
PLL |
LVDS |
9 |
3 |
212.5 |
PLL |
LVPECL |
3 |
212.5 |
PLL |
LVPECL |
3 |
212.5 |
PLL |
LVPECL |
10 |
3 |
212.5 |
PLL |
LVDS |
3 |
212.5 |
PLL |
LVDS |
3 |
212.5 |
PLL |
LVDS |
11 |
25 |
100 |
PLL |
HCSL |
100 |
25 |
PLL |
LVDS |
100 |
25 |
PLL |
LVCMOS |
12 |
25 |
100 |
PLL |
HCSL |
100 |
25 |
PLL |
LVDS |
100 |
25 |
PLL |
LVCMOS |
13 |
17 |
100 |
PLL |
HCSL |
17 |
100 |
PLL |
HCSL |
17 |
100 |
PLL |
HCSL |
14 |
17 |
100 |
PLL |
HCSL |
17 |
100 |
PLL |
HCSL |
17 |
100 |
PLL |
HCSL |
15 |
34 |
50 |
PLL |
LVDS |
3 |
566.67 |
PLL |
LVPECL |
16 |
106.25 |
PLL |
LVDS |
16 |
34 |
50 |
PLL |
LVDS |
3 |
566.67 |
PLL |
LVPECL |
16 |
106.25 |
PLL |
LVDS |
17 |
4 |
156.25 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
18 |
4 |
156.25 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
19 |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
20 |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
21 |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
22 |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
23 |
25 |
100 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
24 |
25 |
100 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
25 |
25 |
100 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
26 |
25 |
100 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
27 |
20 |
125 |
PLL |
LVPECL |
25 |
100 |
PLL |
LVCMOS |
100 |
25 |
PLL |
LVCMOS |
28 |
4 |
156.25 |
PLL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
25 |
25 |
PLL |
LVCMOS |
29 |
25 |
25 |
PLL |
LVCMOS |
25 |
25 |
PLL |
LVCMOS |
25 |
25 |
PLL |
LVCMOS |
30 |
8 |
312.5 |
PLL |
LVDS |
25 |
100 |
PLL |
LVDS |
20 |
125 |
PLL |
LVDS |
31 |
25 |
100 |
PLL |
HCSL |
25 |
100 |
PLL |
HCSL |
100 |
25 |
PLL |
LVPECL |
32 |
25 |
100 |
PLL |
LVDS |
25 |
100 |
PLL |
LVDS |
25 |
100 |
PLL |
LVDS |
33 |
4 |
156.25 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
34 |
4 |
156.25 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
35 |
4 |
156.25 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
36 |
4 |
156.25 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
37 |
4 |
156.25 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
38 |
4 |
156.25 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
39 |
4 |
156.25 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
40 |
4 |
156.25 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVCMOS |
41 |
4 |
155.52 |
PLL |
LVPECL |
8 |
77.76 |
PLL |
LVDS |
8 |
77.76 |
PLL |
LVDS |
42 |
4 |
155.52 |
PLL |
LVDS |
8 |
77.76 |
PLL |
LVDS |
8 |
77.76 |
PLL |
LVDS |
43 |
4 |
155.52 |
PLL |
LVDS |
8 |
77.76 |
PLL |
LVDS |
8 |
77.76 |
PLL |
LVDS |
44 |
4 |
155.52 |
PLL |
LVDS |
8 |
77.76 |
PLL |
LVDS |
8 |
77.76 |
PLL |
LVDS |
45 |
4 |
250 |
PLL |
LVPECL |
40 |
25 |
PLL |
LVCMOS |
15 |
66.67 |
PLL |
LVCMOS |
46 |
4 |
250 |
PLL |
LVDS |
40 |
25 |
PLL |
LVCMOS |
15 |
66.67 |
PLL |
LVCMOS |
47 |
10 |
62.5 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
2 |
312.5 |
PLL |
LVPECL |
48 |
10 |
62.5 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
2 |
312.5 |
PLL |
LVDS |
49 |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
50 |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
5 |
125 |
PLL |
LVDS |
51 |
17 |
156.25 |
PLL |
LVPECL |
17 |
156.25 |
PLL |
LVPECL |
17 |
156.25 |
PLL |
LVPECL |
52 |
17 |
156.25 |
PLL |
LVDS |
17 |
156.25 |
PLL |
LVDS |
17 |
156.25 |
PLL |
LVDS |
53 |
2 |
322.265625 |
PLL |
LVPECL |
2 |
322.265625 |
PLL |
LVPECL |
2 |
322.265625 |
PLL |
LVPECL |
54 |
2 |
322.265625 |
PLL |
LVDS |
2 |
322.265625 |
PLL |
LVDS |
2 |
322.265625 |
PLL |
LVDS |
55 |
2 |
322.265625 |
PLL |
LVPECL |
2 |
322.265625 |
PLL |
LVPECL |
2 |
322.265625 |
PLL |
LVPECL |
56 |
2 |
322.265625 |
PLL |
LVDS |
2 |
322.265625 |
PLL |
LVDS |
2 |
322.265625 |
PLL |
LVDS |
57 |
25 |
100 |
PLL |
HCSL |
25 |
100 |
PLL |
HCSL |
25 |
100 |
PLL |
HCSL |
58 |
25 |
100 |
PLL |
HCSL |
25 |
100 |
PLL |
HCSL |
25 |
100 |
PLL |
HCSL |
59 |
2 |
312.5 |
PLL |
LVPECL |
2 |
312.5 |
PLL |
LVPECL |
2 |
312.5 |
PLL |
LVPECL |
60 |
2 |
312.5 |
PLL |
LVPECL |
2 |
312.5 |
PLL |
LVPECL |
2 |
312.5 |
PLL |
LVPECL |
61 |
4 |
156.25 |
PLL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
62 |
4 |
156.25 |
PLL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
4 |
156.25 |
PLL |
LVPECL |
63 |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |
5 |
125 |
PLL |
LVPECL |