JAJSFG7J July   1999  – February 2024 THS4031 , THS4032

PRODUCTION DATA  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Pin Configuration and Functions
6. 5 Specifications
   1. 5.1  Absolute Maximum Ratings
   2. 5.2  ESD Ratings
   3. 5.3  Recommended Operating Conditions
   4. 5.4  Thermal Information: THS4031
   5. 5.5  Thermal Information: THS4032
   6. 5.6  Electrical Characteristics: THS4031, RL = 150 Ω
   7. 5.7  Electrical Characteristics: THS4031, RL = 1 kΩ
   8. 5.8  Electrical Characteristics: THS4032, RL = 150 Ω
   9. 5.9  Electrical Characteristics: THS4032, RL = 1 kΩ
   10. 5.10 Typical Characteristics: THS4031
   11. 5.11 Typical Characteristics: THS4032
7. 6 Detailed Description
   1. 6.1 Overview
   2. 6.2 Functional Block Diagrams
   3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
   4. 6.4 Device Functional Modes
8. 7 Application and Implementation
   1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-pass Filter Configurations
   2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
         1. 7.2.2.1 Selection of Multiplexer
         2. 7.2.2.2 Signal Source
         3. 7.2.2.3 Driving Amplifier
         4. 7.2.2.4 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
   3. 7.3 Power Supply Recommendations
   4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
         1. 7.4.1.1 General PowerPAD™ Design Considerations
      2. 7.4.2 Layout Example
9. 8 Device and Documentation Support
   1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
   2. 8.2 ドキュメントの更新通知を受け取る方法
   3. 8.3 サポート・リソース
   4. 8.4 商標
   5. 8.5 静電気放電に関する注意事項
   6. 8.6 用語集
10. 9 Revision History
11. 10Mechanical, Packaging, and Orderable Information