JAJSHP5A July 2019 – October 2019 TLV320ADC5140
PRODUCTION DATA.
This register is the ASI output channel enable configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASI_OUT_CH1_EN | ASI_OUT_CH2_EN | ASI_OUT_CH3_EN | ASI_OUT_CH4_EN | ASI_OUT_CH5_EN | ASI_OUT_CH6_EN | ASI_OUT_CH7_EN | ASI_OUT_CH8_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ASI_OUT_CH1_EN | R/W | 0h | ASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition 1d = Channel 1 output slot is enabled |
6 | ASI_OUT_CH2_EN | R/W | 0h | ASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition 1d = Channel 2 output slot is enabled |
5 | ASI_OUT_CH3_EN | R/W | 0h | ASI output channel 3 enable setting.
0d = Channel 3 output slot is in a tri-state condition 1d = Channel 3 output slot is enabled |
4 | ASI_OUT_CH4_EN | R/W | 0h | ASI output channel 4 enable setting.
0d = Channel 4 output slot is in a tri-state condition 1d = Channel 4 output slot is enabled |
3 | ASI_OUT_CH5_EN | R/W | 0h | ASI output channel 5 enable setting.
0d = Channel 5 output slot is in a tri-state condition 1d = Channel 5 output slot is enabled |
2 | ASI_OUT_CH6_EN | R/W | 0h | ASI output channel 6 enable setting.
0d = Channel 6 output slot is in a tri-state condition 1d = Channel 6 output slot is enabled |
1 | ASI_OUT_CH7_EN | R/W | 0h | ASI output channel 7 enable setting.
0d = Channel 7 output slot is in a tri-state condition 1d = Channel 7 output slot is enabled |
0 | ASI_OUT_CH8_EN | R/W | 0h | ASI output channel 8 enable setting.
0d = Channel 8 output slot is in a tri-state condition 1d = Channel 8 output slot is enabled |