JAJSHP5A July 2019 – October 2019 TLV320ADC5140
PRODUCTION DATA.
This register is the software reset register. Asserting a software reset places all register values in their default power-on-reset (POR) state.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SW_RESET | ||||||
R-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | Reserved | R | 0h | Reserved |
0 | SW_RESET | R/W | 0h | Software reset. This bit is self clearing.
0d = Do not reset 1d = Reset |