JAJSKU4B December   2020  – July 2022 ADC3664

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Bit Mapper
        3. 8.3.5.3 Output Interface/Mode Configuration
          1. 8.3.5.3.1 Configuration Example
        4. 8.3.5.4 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

8.6.1 Detailed Register Description

Figure 8-45 Register 0x00
76543210
0000000RESET
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-13 Register 0x00 Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0RESETR/W0This bit resets all internal registers to the default values and self clears to 0.
Figure 8-46 Register 0x07
76543210
OP IF MAPPER0OP IF ENOP IF SEL
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-14 Register 0x07 Field Descriptions
BitFieldTypeResetDescription
7-5OP IF MAPPERR/W000Output interface mapper. This register contains the proper output interface bit mapping for the different interfaces. The interface bit mapping is internally loaded from e-fuses and also requires a fuse load command to go into effect (0x13, D0). Register 0x07 along with the E-Fuse Load (0x13, D0) needs to be loaded first in the programming sequence since the E-Fuse load resets the SPI writes.
After initial reset the default output interface variant is loaded automatically from fuse internally. However when reading back this register reads 000 until a value is written using SPI.
001: 2-wire, 18 and 14-bit
010: 2-wire, 16-bit
011: 1-wire
100: 0.5-wire
others: not used
40R/W0Must write 0
3OP IF ENR/W0Enables changing the default output interface mode (D2-D0).
2-0OP IF SELR/W000Selection of the output interface mode. OP IF EN (D3) needs to be enabled also.
After initial reset the default output interface is loaded automatically from fuse internally. However when reading back this register reads 000 until a value is written using SPI.
011: 2-wire
100: 1-wire
101: 0.5-wire
others: not used
Figure 8-47 Register 0x08
76543210
00PDN CLKBUFPDN REFAMP0PDN APDN BPDN GLOBAL
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-15 Register 0x08 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5PDN CLKBUFR/W0Powers down sampling clock buffer
0: Clock buffer enabled
1: Clock buffer powered down
4PDN REFAMPR/W0Powers down internal reference gain amplifier
0: REFAMP enabled
1: REFAMP powered down
30R/W0Must write 0
2PDN AR/W0Powers down ADC channel A
0: ADC channel A enabled
1: ADC channel A powered down
1PDN BR/W0Powers down ADC channel B
0: ADC channel B enabled
1: ADC channel B powered down
0PDN GLOBALR/W0Global power down via SPI
0: Global power disabled
1: Global power down enabled. Power down mask (register 0x0D) determines which internal blocks are powered down.
Figure 8-48 Register 0x09
76543210
00PDN FCLKOUTPDN DCLKOUTPDN DA0PDN DA1PDN DB0PDN DB1
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-16 Register 0x09 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5PDN FCLKOUTR/W0Powers down frame clock (FCLK) LVDS output buffer
0: FCLK output buffer enabled
1: FCLK output buffer powered down
4PDN DCLKOUTR/W0Powers down DCLK LVDS output buffer
0: DCLK output buffer enabled
1: DCLK output buffer powered down
3PDN DA1R/W0Powers down LVDS output buffer for channel A, lane 1. NOT powered down automatically in 1-wire and 1/2-wire mode.
0: DA1 LVDS output buffer enabled
1: DA1 LVDS output buffer powered down
2PDN DA0R/W0Powers down LVDS output buffer for channel A, lane 0.
0: DA0 LVDS output buffer enabled
1: DA0 LVDS output buffer powered down
1PDN DB1R/W0Powers down LVDS output buffer for channel B, lane 1. NOT powered down automatically in 1-wire and 1/2-wire mode.
0: DB1 LVDS output buffer enabled
1: DB1 LVDS output buffer powered down
0PDN DB0R/W0Powers down LVDS output buffer for channel B, lane 0. NOT powered down automatically in 1/2-wire mode.
0: DB0 LVDS output buffer enabled
1: DB0 LVDS output buffer powered down
Figure 8-49 Register 0x0D (PDN GLOBAL MASK)
76543210
0000MASK CLKBUFMASK REFAMPMASK BG DIS0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-17 Register 0x0D Field Descriptions
BitFieldTypeResetDescription
7-40R/W0Must write 0
3MASK CLKBUFR/W0Global power down mask control for sampling clock input buffer.
0: Clock buffer will get powered down when global power down is exercised.
1: Clock buffer will NOT get powered down when global power down is exercised.
2MASK REFAMPR/W0Global power down mask control for reference amplifier.
0: Reference amplifier will get powered down when global power down is exercised.
1: Reference amplifier will NOT get powered down when global power down is exercised.
1MASK BG DISR/W0Global power down mask control for internal 1.2V bandgap voltage reference. Setting this bit reduces power consumption in global power down mode but increases the wake up time. See the power down option overview.
0: Internal 1.2V bandgap voltage reference will NOT get powered down when global power down is exercised.
1: Internal 1.2V bandgap voltage reference will get powered down when global power down is exercised.
00R/W0Must write 0
Figure 8-50 Register 0x0E
76543210
SYNC PIN ENSPI SYNCSPI SYNC EN0REF CTLREF SELSE CLK EN
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-18 Register 0x0E Field Descriptions
BitFieldTypeResetDescription
7SYNC PIN ENR/W0This bit controls the functionality of the SYNC/PDN pin.
0: SYNC/PDN pin exercises global power down mode when pin is pulled high.
1: SYNC/PDN pin issues the SYNC command when pin is pulled high.
6SPI SYNCR/W0Toggling this bit issues the SYNC command using the SPI register write. SYNC using SPI must be enabled as well (D5). This bit doesn't self reset to 0.
0: Normal operation
1: SYNC command issued.
5SPI SYNC ENR/W0This bit enables synchronization using SPI instead of the SYNC/PDN pin.
0: Synchronization using SPI register bit disabled.
1: Synchronization using SPI register bit enabled.
40R/W0Must write 0
3REF CTLR/W0This bit determines if the REFBUF pin controls the voltage reference selection or the SPI register (D2-D1).
0: The REFBUF pin selects the voltage reference option.
1: Voltage reference is selected using SPI (D2-D1) and single ended clock using D0.
2-1REF SELR/W00Selects of the voltage reference option. REF CTRL (D3) must be set to 1.
00: Internal reference
01: External voltage reference (1.2V) using internal reference buffer (REFBUF)
10: External voltage reference
11: not used
0SE CLK ENR/W0Selects single ended clock input and powers down the differential sampling clock input buffer. REF CRTL (D3) must be set to 1.
0: Differential clock input
1: Single ended clock input
Figure 8-51 Register 0x11
76543210
00SE ASE B0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-19 Register 0x11 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5SE AR/W0This bit enables single ended analog input, channel A. In this mode the SNR is reduced by 3-dB.
0: Differential input
1: Single ended input
4SE BR/W0This bit enables single ended analog input, channel B. In this mode the SNR is reduced by 3-dB.
0: Differential input
1: Single ended input
3-00R/W0Must write 0
Figure 8-52 Register 0x13
76543210
000000E-FUSE LD
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-20 Register 0x13 Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0E-FUSE LDR/W0This register bit loads the internal bit mapping for different interfaces. After setting the interface in register 0x07, this E-FUSE LD bit needs to be set to 1 and reset to 0 for loading to go into effect. Register 0x07 along with the E-Fuse Load (0x13, D0) needs to be loaded first in the programming sequence since the E-Fuse load resets the SPI writes.
0: E-FUSE LOAD set
1: E-FUSE LOAD reset
Figure 8-53 Register 0x14/15/16
76543210
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]
TEST PAT BTEST PAT ACUSTOM PAT [17:16]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-21 Register 0x14/15/16 Field Descriptions
BitFieldTypeResetDescription
7-0CUSTOM PAT [17:0]R/W00000000This register is used for two purposes:
  • It sets the constant custom pattern starting from MSB
  • It sets the RAMP pattern increment step size.

00001: Ramp pattern for 18-bit ADC
00100: Ramp pattern for 16-bit ADC
10000: Ramp pattern for 14-bit ADC
7-5TEST PAT BR/W000Enables test pattern output mode for channel B (NOTE: The test pattern is set prior to the bit mapper and is based on native resolution of the ADC starting from the MSB). These work in either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register 0x14/15/16.
others: not used
4-2TEST PAT AR/W000Enables test pattern output mode for channel A (NOTE: The test pattern is set prior to the bit mapper and is based on native resolution of the ADC starting from the MSB). These work in either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register 0x14/15/16.
others: not used
Figure 8-54 Register 0x19
76543210
FCLK SRC00FCLK DIV000TOG FCLK
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-22 Register 0x19 Field Descriptions
BitFieldTypeResetDescription
7FCLK SRCR/W0User has to select if FCLK signal comes from ADC or from DDC block. Here real decimation is treated same as bypass mode
0: FCLK generated from ADC. FCLK SRC set to 0 for DDC bypass, real decimation mode and 1/2-w complex decimation mode.
1: FCLK generated from DDC block. In complex decimation mode only this bit needs to be set for 2-w and 1-w output interface mode but NOT for 1/2-w mode.
6-50R/W0Must write 0
4FCLK DIVR/W0This bit needs to be set to 1 for 2-w output mode in bypass mode only (non decimation).
0: All output interface modes except 2-w bypass mode..
1: 2-w output interface mode.
3-10R/W0Must write 0
0TOG FCLKR/W0This bit adjusts the FCLK signal appropriately for 1/2-wire mode where FCLK is stretched to cover channel A and channel B. This bit ONLY needs to be set in 1/2-wire mode with complex decimation mode.
0: all other modes.
1: FCLK for 1/2-wire complex decimation mode.
Table 8-23 Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface
BYPASS/DECIMATIONSERIAL INTERFACEFCLK SRCFCLK DIVTOG FCLK
Decimation Bypass/ Real Decimation2-wire010
1-wire000
1/2-wire000
Complex Decimation2-wire100
1-wire100
1/2-wire001
Figure 8-55 Register 0x1A
76543210
0LVDS ½ SWING000000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-24 Register 0x1A Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6LVDS ½ SWINGR/W0This bit reduces the LVDS output current from 3.5mA to 1.75mA which reduces power consumption.
5-00R/W0Must write 0
Figure 8-56 Register 0x1B
76543210
MAPPER EN20B ENBIT MAPPER RES000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-25 Register 0x1B Field Descriptions
BitFieldTypeResetDescription
7MAPPER ENR/W0This bit enables changing the resolution of the output (including output serialization factor) in bypass mode only. This bit is not needed for 20-bit resolution output.
0: Output bit mapper disabled.
1: Output bit mapper enabled.
620B ENR/W0This bit enables 20-bit output resolution which can be useful for very high decimation settings so that quantization noise doesn't impact the ADC performance.
0: 20-bit output resolution disabled.
1: 20-bit output resolution enabled.
5-3BIT MAPPER RESR/W000Sets the output resolution using the bit mapper. MAPPER EN bit (D6) needs to be enabled when operating in bypass mode..
000: 18 bit
001: 16 bit
010: 14 bit
all others, n/a
2-00R/W0Must write 0
Table 8-26 Register Settings for Output Bit Mapper vs Operating Mode
BYPASS/DECIMATIONOUTPUT RESOLUTIONMAPPER EN (D7)BIT MAPPER RES (D5-D3)
Decimation BypassResolution Change1000: 18-bit
001: 16-bit
010: 14-bit
Real DecimationResolution Change (default 18-bit)0
Complex Decimation0
Figure 8-57 Register 0x1E
76543210
0000LVDS DATA DELLVDS DCLK DEL
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-27 Register 0x1E Field Descriptions
BitFieldTypeResetDescription
7-40R/W0Must write 0
3-2LVDS DATA DELR/W00These bits adjust the output timing of the SLVDS output data.
00: no delay
01: Data advanced by 50 ps
10: Data delayed by 50 ps
11: Data delayed by 100 ps
1-0LVDS DCLK DELR/W00These bits adjust the output timing of the SLVDS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
Figure 8-58 Register 0x20/21/22
76543210
FCLK PAT [7:0]
FCLK PAT [15:8]
0000FCLK PAT [19:16]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-28 Register 0x20/21/22 Field Descriptions
BitFieldTypeResetDescription
7-0FCLK PAT [19:0]R/W0xFFC00These bits can adjust the duty cycle of the FCLK. In decimation bypass mode the FCLK pattern gets adjusted automatically for the different output resolutions. Table 8-29 shows the proper FCLK pattern values for 1-wire and 1/2-wire in real/complex decimation.
Table 8-29 FCLK Pattern for different resolution based on interface
DECIMATIONOUTPUT RESOLUTION2-WIRE1-WIRE1/2-WIRE
REAL DECIMATION14-bitUse Default0xFE000Use Default
16-bit0xFF000
18-bit0xFF800
20-bit0xFFC00
COMPLEX DECIMATION14-bit0xFFFFF0xFFFFF
16-bit
18-bit
20-bit
Figure 8-59 Register 0x24
76543210
00CH AVG ENDDC MUXDIG BYPDDC EN0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-30 Register 0x24 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5CH AVG ENR/W0Averages the output of ADC channel A and channel B together. The DDC MUX has to be enabled and set to '11'. The decimation filter needs to be enabled and set to bypass (fullrate output) or decimation and DIG BYP set to 1.
0: Channel averaging feature disabled
1: Output of channel A and channel B are averaged: (A+B)/2.
4-3DDC MUXR/W0Configures DDC MUX in front of the decimation filter.
00: ADC channel A connected to DDC A; ADC Channel B connected to DDC B
01: ADC channel A connected to DDC A and DDC B.
10: ADC channel B connected to DDC A and DDC B.
11: Output of ADC averaging block (see CH AVG EN) given to DDC A and DDC B.
2DIG BYPR/W0This bit needs to be set to enable digital features block which includes decimation.
0: Digital feature block bypassed - lowest latency
1: Data path includes digital features
1DDC ENR/W0Enables internal decimation filter for both channels
0: DDC disabled.
1: DDC enabled.
00R/W0Must write 0
GUID-20200903-CA0I-9K0P-07KQ-DWLHB50H4GW2-low.gifFigure 8-60 Register control for digital features
Figure 8-61 Register 0x25
76543210
DDC MUX ENDECIMATIONREAL OUT00MIX PHASE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-31 Register 0x25 Field Descriptions
BitFieldTypeResetDescription
7DDC MUX ENR/W0Enables the digital mux between ADCs and decimation filters. This bit is required for DDC mux settings in register 0x24 (D4, D3) to go into effect.
0: DDC mux disabled
1: DDC mux enabled
6-4DECIMATIONR/W000Complex decimation setting. This applies to both channels.
000: Bypass mode (no decimation)
001: Decimation by 2
010: Decimation by 4
011: Decimation by 8
100: Decimation by 16
101: Decimation by 32
others: not used
3REAL OUTR/W0This bit selects real output decimation. This mode applies to both channels. In this mode, the decimation filter is a low pass filter and no complex mixing is performed to reduce power consumption. For maximum power savings the NCO in this case should be set to 0.
0: Complex decimation
1: Real decimation
2-10R/W0Must write 0
0MIX PHASER/W0This bit used to invert the NCO phase
0: NCO phase as is.
1: NCO phase inverted.
Figure 8-62 Register 0x26
76543210
MIX GAIN AMIX RES AFS/4 MIX AMIX GAIN BMIX RES BFS/4 MIX B
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-32 Register 0x26 Field Descriptions
BitFieldTypeResetDescription
7-6MIX GAIN AR/W00This bit applies a 0, 3 or 6-dB digital gain to the output of digital mixer to compensate for the mixing loss for channel A.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
5MIX RES AR/W0Toggling this bit resets the NCO phase of channel A and loads the new NCO frequency. This bit does not self reset.
4FS/4 MIX AR/W0Enables FS/4 mixing for DDC A (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
3-2MIX GAIN BR/W00This bit applies a 0, 3 or 6-dB digital gain to the output of digital mixer to compensate for the mixing loss for channel B.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
1MIX RES BR/W0Toggling this bit resets the NCO phase of channel B and loads the new NCO frequency. This bit does not self reset.
0FS/4 MIX BR/W0Enables FS/4 mixing for DDC B (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
Figure 8-63 Register 0x27
76543210
000OP ORDER AQ-DEL AFS/4 MIX PH A00
DDC OFFSET A [9:2]
0DDC OFFSET A [16:10]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-33 Register 0x27 Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4OP ORDER AR/W0Swaps the I and Q output order for channel A
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3Q-DEL AR/W0This delays the Q-sample output of channel A by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2FS/4 MIX PH AR/W0Inverts the mixer phase for channel A when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-00R/W0Must write 0
Figure 8-64 Register 0x2A/B/C/D
76543210
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-34 Register 0x2A/2B/2C/2D Field Descriptions
BitFieldTypeResetDescription
7-0NCO A [31:0]R/W0Sets the 32 bit NCO value for decimation filter channel A. The NCO value is fNCO× 232/FS
In real decimation mode these registers are automatically set to 0.
Figure 8-65 Register 0x2E
76543210
000OP ORDER BQ-DEL BFS/4 MIX PH B00
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-35 Register 0x2E Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4OP ORDER BR/W0Swaps the I and Q output order for channel B
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3Q-DEL BR/W0This delays the Q-sample output of channel B by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2FS/4 MIX PH BR/W0Inverts the mixer phase for channel B when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-00R/W0Must write 0
Figure 8-66 Register 0x31/32/33/34
76543210
NCO B [7:0]
NCO B [15:8]
NCO B [23:16]
NCO B [31:24]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-36 Register 0x31/32/33/34 Field Descriptions
BitFieldTypeResetDescription
7-0NCO B [31:0]R/W0Sets the 32 bit NCO value for decimation filter channel B. The NCO value is fNCO× 232/FS
In real decimation mode these registers are automatically set to 0.
Figure 8-67 Register 0x39..0x60
76543210
OUTPUT BIT MAPPER CHA
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-37 Register 0x39..0x60 Field Descriptions
BitFieldTypeResetDescription
7-0OUTPUT BIT MAPPER CHAR/W0These registers are used to reorder the output data bus. See the Section 8.3.5.2 on how to program it.
Figure 8-68 Register 0x61..0x88
76543210
OUTPUT BIT MAPPER CHB
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-38 Register 0x61..0x88 Field Descriptions
BitFieldTypeResetDescription
7-0OUTPUT BIT MAPPER CHBR/W0These registers are used to reorder the output data bus of channel B. See the Section 8.3.5.2 on how to program it.
Figure 8-69 Register 0x8F
76543210
000000FORMAT A0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-39 Register 0x8F Field Descriptions
BitFieldTypeResetDescription
7-20R/W0Must write 0
1FORMAT AR/W0This bit sets the output data format for channel A. Digital bypass register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
00R/W0Must write 0
Figure 8-70 Register 0x92
76543210
000000FORMAT B0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-40 Register 0x92 Field Descriptions
BitFieldTypeResetDescription
7-20R/W0Must write 0
1FORMAT BR/W0This bit sets the output data format for channel B. Digital bypass register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
00R/W0Must write 0