SBAS888A December 2020 – August 2021
PRODUCTION DATA
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 9-6.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
t1 | Power-on delay: delay from power up to logic level of REFBUF pin | 2 | ms | ||
t2 | Delay from REFBUF pin logic level to RESET rising edge | 100 | ns | ||
t4 | RESET pulse width | 1 | us | ||
t5 | Delay from RESET disable to SEN active | ~ 200000 | clock cycles |