SBAU442 December   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Board Overview
    2. 2.2 Required Equipment
    3. 2.3 Hardware Setup
  9. 3Software
    1. 3.1 Software Setup
  10. 4Implementation Results
    1. 4.1 Evaluation Setup
    2. 4.2 EVM Capture
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7References

Evaluation Setup

Once the software setup and hardware setups are completed. Follow these steps to get a capture on the ADC3910D125EVM:

  1. Connect a bandpass filtered 125 MHz clock signal to the ADC.
  2. Connected a bandpass filtered 10.097503662MHz input signal to either ADC input.
  3. Launch a PowerShell terminal and change current directory to the location of the ADC3910D125EVM_API_Rev0.1. From within the ADC3910D125EVM_API_Rev0.1 folder, run the following command: pip install -r requirements.txt.
    1. This installs the required python packages to run the provided software files.
  4. Launch the tcl_client.tcl file, found in the ADC3910D125EVM_API_Rev0.1 folder, in a text editor and update the path in line six to your path.
    GUID-20231215-SS0I-XNJP-VT8H-PTHVQLDHB47X-low.svg Figure 4-1 Path that needs to be edited in "tcl_client.tcl"
  5. Launch and run ADC3910D125EVM_API_Rev0.1.py file provided in the software suite.
    1. By default, this file is setup to provide a hardware and software reset to the ADC.
    2. The ADC is placed in the default dual-channel, 10-bit, low latency, DDR interface mode.
    3. R67 can be probed to confirm that DCLK is active.
  6. Launch Vivado Lab 2023.2:
    1. Click on Open Hardware Manager.
    2. Click on Open target at the top with the green background.
    3. Click on Auto Connect from the pop up menu.
      1. This connects to the xc7a100t_0 FPGA.
    4. Right-click xc7a100t_0, then select Program Device in the pop-up menu.
      GUID-20231215-SS0I-K6NN-K73Q-P1SVKKZZBLFW-low.svg Figure 4-2 Programming FPGA Menu
    5. In the pop up menu click on ... on the Bitstream file row and navigate to the bitfiles folder in the ADC3910D125EVM_API_Rev0.1 folder. Select the 10b_DDR.bit file.
      GUID-20231215-SS0I-WLMP-1PNT-4B49HS67KP7G-low.svg Figure 4-3 Bitfiles to Program FPGA
    6. Click on Program
      1. There is a new window now called hw_ila_1.
    7. In the hw_ila_1 waveform view, select all the values and right click. In the pop-up menu, hover over Radix and in the next pop-up menu, select Signed Decimal.
      GUID-20231215-SS0I-M3DF-9K2J-SHQPL1MJQLXQ-low.svg Figure 4-4 Changing ILA radix to signed decimal
    8. In the Tcl Console command line, change the current directory to the location of the ADC3910D125EVM_API_Rev0.1 folder.
      GUID-20231215-SS0I-FSXF-ZDDL-KKRVHW9BCMQD-low.svg Figure 4-5 Change Current Directory in Vivado Lab 2023.2
    1. Launch and run py_server.py from ADC3910D125EVM_API_Rev0.1 folder.
      1. After the running the file, STARTING THE SERVER.... is printed by the python terminal.
    2. Launch HSDC Pro, click OK in the first pop-up menu and click OK again in the next pop-up window.
    3. In Vivado™ Lab 2023.2 in the Tcl Console type the following command: source ./tcl_client.tcl
    4. Now, the py_server.py python terminal shows Input a command.
      1. The available commands are Capture and Quit.
    5. In the py_server.py python terminal, type Capture (this is case sensitive).
    6. In HSDC Pro, an FFT of the input signals needs to be captured.