SBAU442 December 2023
The ADC3910D125EVM allows for evaluation of all ADC39XX versions as the versions are all P2P compatible. By default, the ADC3910D125EVM, has the ADC3910D125 (10-bit, 125MSPS). The EVM is configured to receive external single-ended analog inputs as the EVM includes baluns for single-ended to differential conversion. The sample clock is also sourced externally and is single-ended LVCMOS.
To capture data from the ADC3910D125EVM, the EVM is connected to a TSW1418EVM through an FMC connector. The TSW1418EVM has an AMD Atrix-7 FPGA to capture the ADC3910D125EVM output. The ADC data, captured by the FPGA, is then transferred to the PC and displayed in HSDC Pro.