SBOU229A August   2019  – April 2022 THS6222

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 EVM Specifications
  3. 2Power Connections
    1. 2.1 Split-Supply Operation
    2. 2.2 Single-Supply Operation
  4. 3Input and Output Connections
    1. 3.1 Bias Mode Control Pins
    2. 3.2 IREF Pin Connection
    3. 3.3 Optional VCM Pin Connection
  5. 4Board Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  7. 6Related Documentation
  8. 7Revision History

Board Layout

The layer plots of Figure 4-1 to Figure 4-4 illustrate the board layers in top to bottom order.

GUID-66FA52DF-C71D-4640-B226-B56533954D55-low.pngFigure 4-1 Top Layer
GUID-64AA42D8-DA0B-4F50-A400-AA1CA8B1F1B8-low.pngFigure 4-3 Power Layer
GUID-CB9D3CA4-A07C-44DF-A9E8-C837B549ECA5-low.pngFigure 4-2 Ground Layer
GUID-036E15CC-F5B5-4AB7-B708-FDF71FBA830C-low.pngFigure 4-4 Bottom Layer